PIC32MX575F256L-80I/PF Microchip Technology, PIC32MX575F256L-80I/PF Datasheet
PIC32MX575F256L-80I/PF
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PIC32MX575F256L-80I/PF Summary of contents
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... PIC32MX Device External CPU Programmer On-Chip Memory © 2010 Microchip Technology Inc. PIC32MX All PIC32MX devices provide two physical interfaces to the external programmer tool: • 2-wire In-Circuit Serial Programming™ (ICSP™) • 4-wire Joint Test Action Group (JTAG) See 4.0 “Connecting to the Device” for more information ...
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... Executive (PE)” for more information. 7. Download the Block of Data to Program. All methods, with or without the PE, must down- load the desired programming data into a block of memory in RAM. See 12.0 “Downloading a Data Block” for more information. © 2010 Microchip Technology Inc. before ...
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... Exit the Programming mode. The newly programmed data is not effective until either power is removed and reapplied to the target device or an exit programming sequence is performed. See 15.0 “Exiting Programming Mode” for more information. © 2010 Microchip Technology Inc. PIC32MX DS61145G-page 3 ...
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... TDO is tri-stated. Pin Type Pin Description P Programming Enable I Enable for On-Chip Voltage Regulator P Power Supply P Ground P Regulated Power Supply for Core I Test Data In O Test Data Out I Test Clock I Test Mode State P = Power ) and ground DD © 2010 Microchip Technology Inc. ...
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... PGD2 PGD Legend Input O = Output Note 1: All power supply and ground pins must be connected, including analog supplies (AV © 2010 Microchip Technology Inc. The regulator provides power to the core from the other V pins. A low ESR capacitor (e.g., a tantalum DD capacitor) must be connected to the V (Figure 4-2) ...
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... Each erase block, or page, contains 1K instructions (4 Kbytes), and each program block, or row, contains 128 instructions (512 bytes). - The last four implemented program memory locations in BFM are reserved for the device Configuration registers. © 2010 Microchip Technology Inc. ...
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... PIC32MX664F064H PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX320F128H PIC32MX564F128H PIC32MX664F128H PIC32MX764F128H PIC32MX320F128L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L PIC32MX340F256H PIC32MX575F256H PIC32MX675F256H PIC32MX775F256H PIC32MX360F256L PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512H PIC32MX675F512H PIC32MX695F512H PIC32MX775F512H PIC32MX795F512H PIC32MX360F512L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L © 2010 Microchip Technology Inc. Boot Flash Memory Address (Bytes) ...
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... TCK. TDO data is valid for a chip-specific time after the falling edge of TCK (refer to Figure 5-3). FIGURE 5-3: 4-WIRE JTAG INTERFACE TCK ‘0’ ‘1’ ‘1’ TMS TDI TDO DS61145G-page 8 ‘0’ ‘1’ iMSb iLSb oLSb oMSb ‘0’ ‘1’ © 2010 Microchip Technology Inc. ...
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... TMS TDI TDO PGC PGD © 2010 Microchip Technology Inc. of PGC, while TDO is driven on the falling edge of PGC. 4-Phase mode is used for both read and write data transfers. 5.2.2 2-PHASE ICSP In 2-Phase ICSP mode, the TMS and TDI device pins are multiplexed into PGD in 2 clocks (see Figure 5-5). The LSb is shifted first ...
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... The value of mode is clocked into the device on signal TMS. TDI is set to a ‘0’ and TDO is ignored. Restrictions: None. Example: SetMode (6’b011111) Mode = 6’b011111 ‘1’ ‘1’ ‘1’ ‘1’ Mode = 6’b011111 TDO = 1 TDI = 0 TMS = 0 ‘0’ TDO = X © 2010 Microchip Technology Inc. ...
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... TMS TDI TDO FIGURE 6-4: SendCommand 2-WIRE Command (5’h07) + TMS = 0 TMS Header = 1100 PGC PGD TDI = 0 TDO = X TMS = 1 TDI=iLSb © 2010 Microchip Technology Inc. Restrictions: None. Example: SendCommand (5’h07) Command = 5’h07 Command (MSb) + TMS = 1 ‘0’ ‘1’ iMSb iLSb X 1 ...
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... TMS Header = 100 TDI = 0 TMS = 0 TDO = X X Data (MSb) + TMS Footer = 1 TDI = iMSb TMS = 1 TDO = ... TMS Footer = 10 TDI = 0 TMS = 0 TDO = X X TMS Footer = 10 ‘0’ ‘1’ TDI = 0 TMS = 0 TDO = oLSb X © 2010 Microchip Technology Inc. ...
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... TMS Header = 100 PGC PGD TDI = TDI = 0 TMS = 1 X © 2010 Microchip Technology Inc. 3. TMS Footer = 10 is clocked in to return the TAP controller to the Run/Test Idle state. Restrictions: The SendCommand (ETAP_FASTDATA) must be sent first to select the Fastdata register, as shown in Example 6-1. See Table 19-4 for a detailed descriptions of commands ...
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... TMS Footer = 10 TDI = 0 TMS = 1 TDO = X DS61145G-page 14 TMS Header = 100 TDI = 0 TMS = 0 TDO = TDI = 0 X Data (31’h12) + TMS = 0 TDI = iLSb TMS = 0 TDO = oLSb+1 TDI = 0 TMS = 0 TDO = X TMS = 0 TDO = oPrAcc Data (MSb) + TMS Footer = 1 TDI = iMSb TMS = 1 TDO = X © 2010 Microchip Technology Inc. ...
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... Wait until CPU is ready // Check if Processor Access bit (bit 18) is set do { controlVal = XferData(32’h0x0004C000); } while( PrAcc(contorlVal<18>) is not ‘1’ Select Data Register SendCommand(ETAP_DATA); // Send the instruction XferData(instruction); // Tell CPU to execute instruction SendCommand(ETAP_CONTROL); XferData(32’h0x0000C000); } © 2010 Microchip Technology Inc. PIC32MX DS61145G-page 15 ...
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... Upon successful entry, the program memory can be accessed and programmed in serial fashion. While in Programming mode, all unused I/Os are placed in the high-impedance state Program/Verify Entry Code = 0x4D434850 ... b31 b30 b29 b28 b27 b3 P2B P2A , PIC32MX devices. There After IH must be IH P17 © 2010 Microchip Technology Inc. ...
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... XferData (MCHP_STATUS) No FCBUSY = 0 CFGRDY = 1 Yes Done © 2010 Microchip Technology Inc. 8.1 4-Wire Interface Four-wire JTAG programming is a Mission mode operation and therefore the setup sequence to begin programing should be done while asserting MCLR. Holding the device in Reset prevents the processor from executing instructions or driving ports ...
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... A blank or erased memory location always reads as ‘1’. The device Configuration registers are ignored by the Blank Check. Additionally, all unimplemented memory space should be ignored from the Blank Check. © 2010 Microchip Technology Inc. ...
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... Set MCLR High Select MTAP SendCommand (MTAP_SW_MTAP) Put MTAP in Command Mode SendCommand (MTAP_COMMAND) Release Reset XferData (MCHP_DE_ASSERT_RST) Enable Flash XferData (MCHP_EN_FLASH) 2-Wire © 2010 Microchip Technology Inc. 10.1 4-Wire Interface The following steps are required to enter Serial Execution mode: 1. SendCommand (MTAP_SW_MTAP). 2. SendCommand (MTAP_COMMAND). 3. ...
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... PIC32MX core is as follows: lw a1,64(a0) /* load BMXDMSZ */ sw a1,32(a0) sw a1,48(a0) 0x8C850040 XferInstruction 0xac850020 XferInstruction 0xac850030 XferInstruction Step 4: Set up PIC32MX RAM address for PE. The instruction sequence executed by the PIC32MX core is as follows: lui a0,0xa000 ori a0,a0,0x800 0x3c04a000 XferInstruction 0x34840800 XferInstruction © 2010 Microchip Technology Inc. ...
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... PE Hex file) XferFastData PE_SIZE (Number of 32-bit words of the program block from PE Hex file) XferFastData PE software opcode from PE Hex file (PE Instructions) © 2010 Microchip Technology Inc. PIC32MX TABLE 11-1: DOWNLOAD THE PE Operation Operand Step 8: Jump to the PE. Magic number (0xDEAD0000) instructs the PE_Loader that the PE is completely loaded into the memory ...
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... FIGURE 12-2: DOWNLOADING DATA WITH THE PE Issue Download Data Command Receive Response The following steps are required to download a block of data using the PE: 1. XferFastData (PROGRAM|DATA_SIZE). 2. XferFastData (ADDRESS). 3. response = XferFastData (32’h0x00). © 2010 Microchip Technology Inc. ...
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... INITIATING FLASH WRITE WITHOUT THE PE Unprotect Control Registers Select Write Operation Load Addresses in NVM Registers Unlock Flash Controller Start Operation Done © 2010 Microchip Technology Inc. PIC32MX The following steps are required to initiate a Flash write: 1. XferInstruction (opcode). 2. Repeat Step 1 until the last instruction is transferred to the CPU ...
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... Step 8: Clear NVMCON.WREN bit. ac870004 sw a3,4(a0) Step 9: Check the NVMCON.WRERR bit to ensure that the program sequence completed suc- cessfully error occurs, jump to the error-processing routine. 8c880000 lw t0,0(a0) 30082000 andi t0,zero,0x2000 1500<ERR_PROC> bne t0, $0, <err_proc_offset> 00000000 nop DS61145G-page 24 © 2010 Microchip Technology Inc. ...
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... Reading from Flash memory is performed by executing a series of read accesses from the Fastdata register. Table 19-4 shows the EJTAG programming details, including the address and opcode data for performing processor access operations. © 2010 Microchip Technology Inc. FIGURE 14-2: registers No The following steps are required to verify memory: 1 ...
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... PGDx PGCx The following list provides the actual steps required to exit test mode: 1. SetMode (5’b11111). 2. Assert MCLR. 3. Issue a clock pulse on PGCx. 4. Remove power (if the device is powered). from MCLR 2-WIRE EXIT TEST MODE P9B P15 PGD = Input © 2010 Microchip Technology Inc. ...
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... SendCommand(ETAP_CONTROL); XferData(32’h0x0000C000); // return 32-bit response return response; } © 2010 Microchip Technology Inc. The typical communication sequence between the programmer and the PE is shown in Table 16-1. The sequence begins when the programmer sends the command and optional additional data to the PE, and the PE carries out the command ...
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... Erase pages of code memory from the specified address. 1 Blank Check code. 1 Read the PE software version. 2 Get the CRC of Flash memory. RESPONSE FORMAT 0 Data_Low_1 16 Data_High_N 0 Data_Low_N command that the programmer RESPONSE VALUES Description Command successfully processed Command unsuccessfully processed Command not known (2) . © 2010 Microchip Technology Inc. ...
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... FIGURE 16-4: ROW_PROGRAM RESPONSE 31 Last Command 15 Return Code © 2010 Microchip Technology Inc. 16.2.4 READ COMMAND The READ command instructs the PE to read the instruc- tion Length field that contains the number of 32-bit words of Flash memory, including Configuration Words, starting from the 32-bit address specified by the Addr_Low and Addr_High fields ...
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... This helps the probe and the PE maintain proper synchronization of sending, and receiving, data and responses. Expected Response (1 word): FIGURE 16-8: PROGRAM RESPONSE 31 LSB 16 bits of the destination address of last block 15 Return Code © 2010 Microchip Technology Inc ...
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... FIGURE 16-9: PROGRAM COMMAND ALGORITHM Data is 512 bytes Send 512 bytes (one ROW_SIZE) Receive status (LSB 16 bits of Dest Addr Status Value) © 2010 Microchip Technology Inc. Start Data Data is is larger than 1024 bytes 1024 bytes Block 1 Block 1 Send 512 bytes ...
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... Length TABLE 16-8: CHIP_ERASE FORMAT 0 Field 16 Opcode 0x4 Length Ignored 0 Addr_Low Low 16 bits of 32-bit destination address Addr_High High 16 bits of 32-bit destination address Expected Response (1 word): FIGURE 16-13: CHIP_ERASE RESPONSE 31 Last Command 15 Return Code 16 0 © 2010 Microchip Technology Inc Description 16 0 ...
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... FIGURE 16-15: PAGE_ERASE RESPONSE 31 Last Command 15 Return Code © 2010 Microchip Technology Inc. 16.2.9 BLANK_CHECK COMMAND The BLANK_CHECK command queries the PE to determine whether the contents of code memory and code-protect Configuration bits (GCP and GWRP) are blank (contains all ‘1’s). ...
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... TABLE 16-12: GET_CRC FORMAT Field Opcode 0x8 Address Address where to start calculating the CRC Length Length of buffer on which to calculate the CRC, in number of bytes Expected Response (2 words): FIGURE 16-21: GET_CRC RESPONSE 31 Last Command 15 Return Code 31 CRC_High 15 CRC_Low © 2010 Microchip Technology Inc Description ...
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... Flash programming fails. Expected Response (1 word): FIGURE 16-23: PROGRAM_CLUSTER RESPONSE 31 Last Command 15 Return Code © 2010 Microchip Technology Inc. 16.2.13 GET_DEVICEID COMMAND The GET_DEVICEID command returns the hardware ID of the device. FIGURE 16-24: GET_DEVICEID COMMAND 31 Opcode ...
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... If the value is ‘0’, the PE uses the software CRC calculation method. If the value is ‘1’, the PE uses the hardware CRC unit to calculate the CRC. Expected Response (1 word): FIGURE 16-27: CHANGE_CFG RESPONSE 31 Last Command 15 Return Code DS61145G-page © 2010 Microchip Technology Inc. ...
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... Legend readable bit W = writable bit U = unimplemented bit, read as ‘0’ © 2010 Microchip Technology Inc. 17.2 Mask Values The mask value of a device Configuration is calculated by setting all the unimplemented bits to ‘0’ and all the implemented bits to ‘1’. ...
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... All PIC32MX3XX devices 0x110FF00B All PIC32MX4XX devices 0x110FF00B PIC32MX534F064H 0x110FF00F PIC32MX534F064L 0x110FF00F PIC32MX564F064H 0x110FF00F PIC32MX564F064L 0x110FF00F PIC32MX564F128H 0x110FF00F PIC32MX564F128L 0x110FF00F PIC32MX575F256H 0x110FF00F PIC32MX575F256L 0x110FF00F PIC32MX575F512H 0x110FF00F PIC32MX575F512L 0x110FF00F PIC32MX664F064H 0x110FF00F PIC32MX664F064L 0x110FF00F PIC32MX664F128H 0x110FF00F PIC32MX664F128L 0x110FF00F PIC32MX675F256H 0x110FF00F PIC32MX675F256L 0x110FF00F PIC32MX675F512H ...
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... Yes Checksum (32-bit quantity) = 2’s complement of tmpChecksum Done © 2010 Microchip Technology Inc. Next, the 2’s complement of the summation is calculated. This final 32-bit number is presented as the checksum. The mask values of the device Configuration and Device ID registers are derived as described in the previous section, 17.2 “ ...
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... From Table 17-3, the value of “DCR” is: DCR = 0x000005D4 (32-bit number) POR Default Value & Mask 0x110FF00B 0x110FF00B 0x009FF7A7 0x009FF7A7 0x00070077 0x00070077 0x0000FFFF 0x0000FFFF Total of the 32-bit Summation of Bytes = ) 32-Bit Summation of Mask Bytes 0x0000011B 0x0000023D 0x0000007E 0x000001FE 0x000005D4 © 2010 Microchip Technology Inc. ...
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... Next, the 1’s complement of temp, called temp1, is calculated: temp1 = 1’s complement (temp), which is now equal to 0xF7D83998 4. Finally, the 2’s complement of temp is the checksum: Checksum = 2’s complement (temp), which is Checksum = temp1 + 1, resulting in 0xF7D83999 © 2010 Microchip Technology Inc. POR Default Value Mask & Mask 0x000FF000 ...
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... PIC32MX320F128L FDD23976 PIC32MX340F128L FDD2394A PIC32MX360F256L FBD439D9 PIC32MX360F512L F7D83999 PIC32MX440F128L FDD238BF PIC32MX460F256L FBD4394E PIC32MX460F512L F7D8390E PIC32MX534F064L FED137C6 PIC32MX564F064L FED137B2 PIC32MX564F128L FDD23792 PIC32MX575F256L FBD43893 PIC32MX575F512L F7D837D6 PIC32MX664F064L FED13872 PIC32MX664F128L FDD23852 PIC32MX675F256L FBD43877 PIC32MX675F512L F7D838B6 PIC32MX695F512L F7D838B3 PIC32MX764F128L FDD2380E PIC32MX775F256L FBD438A2 PIC32MX775F512L F7D83863 PIC32MX795F512L F7D83853 © ...
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... Note 1: These bits are not present in PIC32MX3XX and PIC32MX4XX devices. 2: This bit is only present in PIC32MX575F256H, PIC32MX575F256L, PIC32MX575F512H, PIC32MX575F512L, PIC32MX795F512H and PIC32MX795F512L devices. 3: These bits are only present in PIC32MX675F512H, PIC32MX675F512L, PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H and PIC32MX795F512L devices. 4: This bit should be programmed to a ‘1’. ...
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... ICESEL — programmable bit -n = bit value at POR: (‘0’, ‘1’ unknown) r-1 R/P-1 — BWP bit 24 R/P-1 R/P-1 PWP17 PWP16 bit 16 r-1 r-1 — — bit 8 R/P-1 R/P-1 DEBUG1 DEBUG0 bit reserved bit © 2010 Microchip Technology Inc. ...
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... ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pin pair is used 0 = PGEC1/PGED1 pin pair is used bit 2 Reserved: Write as ‘1’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits 11 = In-circuit debugger disabled (forced if device is code protected In-circuit emulator/debugger enabled 01 = Reserved 00 = Reserved © 2010 Microchip Technology Inc. PIC32MX DS61145G-page 45 ...
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... R/P-1 — OSCIOFNC r-1 r-1 R/P-1 — — programmable bit -n = bit value at POR: (‘0’, ‘1’ unknown) r-1 r-1 — — bit 24 R/P-1 R/P-1 bit 16 R/P-1 R/P-1 POSCMOD<1:0> bit 8 R/P-1 R/P-1 FNOSC<2:0> bit reserved bit © 2010 Microchip Technology Inc. ...
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... Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL Module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with divide-by-N with PLL Module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) © 2010 Microchip Technology Inc. PIC32MX DS61145G-page 47 ...
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... R/P-1 — — R/P-1 r-1 R/P-1 — programmable bit -n = bit value at POR: (‘0’, ‘1’ unknown) r-1 r-1 — — bit 24 R/P-1 R/P-1 FPLLODIV<2:0> bit 16 R/P-1 R/P-1 UPLLIDIV<2:0> bit 8 R/P-1 R/P-1 FPLLIDIV<2:0> bit reserved bit © 2010 Microchip Technology Inc. ...
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... Reserved: Maintain as ‘1’ bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider © 2010 Microchip Technology Inc. PIC32MX DS61145G-page 49 ...
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... R/P-x USERID4 USERID3 USERID2 P = programmable bit -n = bit value at POR: (‘0’, ‘1’ unknown) R/P-1 R/P-1 FETHIO FMIIEN bit 24 r-1 r-1 — — bit 16 R/P-x R/P-x USERID9 USERID8 bit 8 R/P-x R/P-x USERID1 USERID0 bit reserved bit © 2010 Microchip Technology Inc. ...
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... R bit bit bit 7 Legend readable bit W = writable bit U = unimplemented bit, read as ‘0’ bit 31-28 VER<3:0>: Revision Identifier bits bit 27-0 DEVID<27:0>: Device ID bits © 2010 Microchip Technology Inc DEVID<27:24> DEVID<23:16> DEVID<15:8> DEVID<7:0> programmable bit -n = bit value at POR: (‘0’, ‘1’ unknown) ...
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... Refer to Table 18-4 for specific write-protection ranges. Note: The PWP bits represent the 1’s complement of the number of protected pages. The amount of program Flash memory available for write protection depends on the family device variant. © 2010 Microchip Technology Inc. ...
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... Device PIC32MX360F512L PIC32MX360F256L PIC32MX340F128L PIC32MX320F128L PIC32MX340F512H PIC32MX340F256H PIC32MX340F128H PIC32MX320F128H PIC32MX320F064H PIC32MX320F032H PIC32MX460F512L PIC32MX460F256L PIC32MX440F128L PIC32MX440F256H PIC32MX440F512H PIC32MX440F128H PIC32MX420F032H © 2010 Microchip Technology Inc. TABLE 18-4: FLASH PROGRAM MEMORY WRITE-PROTECT RANGES PWP Bit Range Size (1) Value (Kbytes) 0xF4 44 0xF3 48 0xF2 52 0xF1 56 0xF0 ...
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... PIC32MX775F512L PIC32MX775F512H PIC32MX775F256L PIC32MX775F256H PIC32MX764F128L PIC32MX764F128H PIC32MX695F512L PIC32MX695F512H PIC32MX675F512L PIC32MX675F512H PIC32MX675F256L PIC32MX675F256H PIC32MX664F128L PIC32MX664F128H PIC32MX664F064L PIC32MX664F064H PIC32MX575F512L PIC32MX575F512H PIC32MX575F256L PIC32MX575F256H PIC32MX564F128L PIC32MX564F128H PIC32MX564F064L PIC32MX564F064H PIC32MX534F064H PIC32MX534F064L DS61145G-page 54 DEVID Register Value Revision ID and Silicon Revision 0x4307053 0x430E053 0x4306053 0x430D053 0x4312053 0x4303053 0x4417053 ...
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... MCHP_DE_ASERT_RST 8’hFC MCHP_ERASE 8’hFE MCHP_FLASH_ENABLE 8’hFD MCHP_FLASH_DISABLE © 2010 Microchip Technology Inc. Description 19.1.1.5 MCHP_FLASH_ENABLE INSTRUCTION MCHP_FLASH_ENABLE sets the FAEN bit, which con- trols processor accesses to the Flash memory. The FAEN bit’s state is returned in the field of the same name. This command has no effect if CPS = 0. This command requires a NOP to complete ...
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... ETAP_EJTAGBOOT 5’h0E ETAP_FASTDATA DS61145G-page 56 0 CFGRDY FCBUSY Description Select Address register. Select Data register. Select EJTAG Control register. Set EjtagBrk, ProbEn and ProbTrap to ‘1’ as Reset value. Selects the Data and Fastdata registers. FAEN DEVRST bit 0 © 2010 Microchip Technology Inc. ...
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... Allows a debug interrupt request • Indicates processor Low-Power mode • Allows implementation-dependent processor and peripheral Resets © 2010 Microchip Technology Inc. PIC32MX The EJTAG Control register is not updated/written in the Update-DR state unless the Reset occurred; that is R (bit 31) is either already ‘0’ written to ‘0’ at OCC the same time ...
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... As noted above, two conditions must be true for the Fastdata access to succeed. These are: • PrAcc must be 1 (i.e., there must be a pending processor access). • The Fastdata operation must use a valid Fastdata area address in the DMSEG segment (0xFF20.0000 to 0xFF20.000F). DS61145G-page 58 © 2010 Microchip Technology Inc. ...
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... Delay between Last PGCx ↓ and MCLR P16 T 8 DLY ↓ Note 1: V must be supplied to the V DDCORE “Power Requirements” for more information must also be supplied to the AV DD ±0. and V , respectively © 2010 Microchip Technology Inc. Min. Max. Units 3.0V 3.60 — 5 — 0 0 — 0.4 1.4 — ...
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... V , respectively DS61145G-page 60 Min. Max. Units — 100 ns 40 — — ns — 500 µs /V pin if the on-chip voltage regulator is disabled. See 4.3 DDCORE CAP pins during programming. AV and Conditions — — — — should always be within SS © 2010 Microchip Technology Inc. ...
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... Boot Page 1 0x1F001FFF Boot Page 2 Debug Page 0x1F002FF0 Configuration Words ( bits) 0x1F002FFF © 2010 Microchip Technology Inc. PIC32MX APPENDIX B: HEX FILE FORMAT Flash programmers process the standard HEX format used by the Microchip development tools. The format ® supported is the Intel HEX32 Format (INHX32). ...
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... Updated DEVID: Device and Revision ID register (see Register 18-5) • Added Device IDs and Revision table (Table 18-5) • Added MCLR High Time (parameter P20) to Table 20-1 • Added Appendix B: “Hex File Format” and Appendix C: “Revision History” © 2010 Microchip Technology Inc. ...
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... Updated the Initiate Flash Row Write Opcodes and instructions (see steps 4, 5 and 6 in Table 13-1) • Added the following devices to Table 5-1, Table 17-1, Table 17-5 and Table 18-1: - PIC32MX534F064H - PIC32MX534F064L - PIC32MX564F064H - PIC32MX564F064L - PIC32MX564F128H - PIC32MX564F128L - PIC32MX575F256L - PIC32MX664F064H - PIC32MX664F064L - PIC32MX664F128H - PIC32MX664F128L - PIC32MX675F256H - PIC32MX675F256L - PIC32MX695F512H - PIC32MX605F512L - PIC32MX764F128H ...
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... PIC32MX NOTES: DS61145G-page 64 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 07/15/10 ...