IC PIC MCU FLASH 8KX14 44TQFP

 

PIC16LF877-04I/PT

Manufacturer Part NumberPIC16LF877-04I/PT
DescriptionIC PIC MCU FLASH 8KX14 44TQFP
ManufacturerMicrochip Technology
SeriesPIC® 16F
PIC16LF877-04I/PT datasheets

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Specifications of PIC16LF877-04I/PT

Core Size8-BitProgram Memory Size14KB (8K x 14)
Core ProcessorPICSpeed4MHz
ConnectivityI²C, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o33Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size368 x 8
Voltage - Supply (vcc/vdd)2 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeExternalOperating Temperature-40°C ~ 85°C
Package / Case44-TQFP, 44-VQFPController Family/seriesPIC16LF
No. Of I/o's33Eeprom Memory Size256Byte
Ram Memory Size368ByteCpu Speed4MHz
No. Of Timers3Lead Free Status / RoHS StatusLead free / RoHS Compliant
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Page 111/218

Download datasheet (4Mb)Embed
PrevNext
10.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
When setting up a Synchronous Slave Reception, fol-
low these steps:
1.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
0Bh, 8Bh,
INTCON
GIE
PEIE
10Bh,18Bh
(1)
0Ch
PIR1
PSPIF
ADIF
18h
RCSTA
SPEN
RX9
1Ah
RCREG
USART Receive Register
(1)
8Ch
PIE1
PSPIE
ADIE
98h
TXSTA
CSRC
TX9
99h
SPBRG
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices, always maintain these bits clear.
2001 Microchip Technology Inc.
2.
If interrupts are desired, set enable bit RCIE.
3.
If 9-bit reception is desired, set bit RX9.
4.
To enable reception, set enable bit CREN.
5.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7.
Read the 8-bit received data by reading the
RCREG register.
8.
If any error occurred, clear the error by clearing
bit CREN.
9.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
T0IE
INTE
RBIE
T0IF
INTF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF 0000 0000 0000 0000
SREN
CREN ADDEN
FERR
OERR
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXEN
SYNC
—
BRGH
TRMT
PIC16F87X
Value on:
Value on all
Bit 0
POR,
other
BOR
RESETS
R0IF
0000 000x
0000 000u
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
DS30292C-page 109

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