IC PIC MCU FLASH 8KX14 44TQFP

 

PIC16LF877-04I/PT

Manufacturer Part NumberPIC16LF877-04I/PT
DescriptionIC PIC MCU FLASH 8KX14 44TQFP
ManufacturerMicrochip Technology
SeriesPIC® 16F
PIC16LF877-04I/PT datasheets

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Specifications of PIC16LF877-04I/PT

Core Size8-BitProgram Memory Size14KB (8K x 14)
Core ProcessorPICSpeed4MHz
ConnectivityI²C, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o33Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size368 x 8
Voltage - Supply (vcc/vdd)2 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeExternalOperating Temperature-40°C ~ 85°C
Package / Case44-TQFP, 44-VQFPController Family/seriesPIC16LF
No. Of I/o's33Eeprom Memory Size256Byte
Ram Memory Size368ByteCpu Speed4MHz
No. Of Timers3Lead Free Status / RoHS StatusLead free / RoHS Compliant
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PIC16F87X
2.2.2.7
PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS 0Dh)
U-0
R/W-0
Reserved
bit 7
bit 7
Unimplemented: Read as '0'
bit 6
Reserved: Always maintain this bit clear
bit 5
Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I2C Master mode
0 = No bus collision has occurred
bit 2-1
Unimplemented: Read as '0'
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
- n = Value at POR
DS30292C-page 24
.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0
R/W-0
R/W-0
U-0
EEIF
BCLIF
W = Writable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
’0’ = Bit is cleared
U-0
R/W-0
CCP2IF
bit 0
x = Bit is unknown
2001 Microchip Technology Inc.