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PIC16LF877-04I/PT
PIC16LF877-04I/PT | |
|---|---|
| Manufacturer Part Number | PIC16LF877-04I/PT |
| Description | IC PIC MCU FLASH 8KX14 44TQFP |
| Manufacturer | Microchip Technology |
| Series | PIC® 16F |
| PIC16LF877-04I/PT datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of PIC16LF877-04I/PT | |||
|---|---|---|---|
| Core Size | 8-Bit | Program Memory Size | 14KB (8K x 14) |
| Core Processor | PIC | Speed | 4MHz |
| Connectivity | I²C, SPI, UART/USART | Peripherals | Brown-out Detect/Reset, POR, PWM, WDT |
| Number Of I /o | 33 | Program Memory Type | FLASH |
| Eeprom Size | 256 x 8 | Ram Size | 368 x 8 |
| Voltage - Supply (vcc/vdd) | 2 V ~ 5.5 V | Data Converters | A/D 8x10b |
| Oscillator Type | External | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 44-TQFP, 44-VQFP | Controller Family/series | PIC16LF |
| No. Of I/o's | 33 | Eeprom Memory Size | 256Byte |
| Ram Memory Size | 368Byte | Cpu Speed | 4MHz |
| No. Of Timers | 3 | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
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PrevNext
2
9.2
MSSP I
C Operation
2
The MSSP module in I
C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits in
hardware, to determine a free bus (multi-master func-
tion). The MSSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Refer to Application Note AN578, "Use of the SSP
2
Module in the I
C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
2
FIGURE 9-5:
I
C SLAVE MODE BLOCK
DIAGRAM
Read
Write
SSPBUF Reg
SCL
Shift
Clock
SSPSR Reg
SDA
MSb
LSb
Match Detect
SSPADD Reg
START and
STOP bit Detect
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
2
ured when the I
C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
The MSSP module has six registers for I
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
2001 Microchip Technology Inc.
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
• I
C Slave mode (7-bit address)
2
• I
C Slave mode (10-bit address)
2
• I
C Master mode, clock = OSC/4 (SSPADD +1)
2
• I
C firmware modes (provided for compatibility to
other mid-range products)
Before selecting any I
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I
tors must be provided externally to the SCL and SDA
pins for the proper operation of the I
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either Master or Slave mode.
When CKE = 1, the levels will conform to the SMBus
Internal
specification. When CKE = 0, the levels will conform to
Data Bus
2
the I
C specification.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address, if the next byte is the com-
pletion of 10-bit address, and if this will be a read or
write data transfer.
SSPBUF is the register to which the transfer data is
written to, or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
Addr Match
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
Set, Reset
complete byte is received before the SSPBUF register
S, P bits
is read, a receiver overflow has occurred and bit
(SSPSTAT Reg)
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
2
C operation.
PIC16F87X
2
C opera-
2
C modes to be selected:
2
C mode, the SCL and SDA pins
2
C mode by setting the
2
C mode. Pull-up resis-
2
C module.
DS30292C-page 73
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