IC PIC MCU FLASH 8KX14 44TQFP

 

PIC16LF877-04I/PT

Manufacturer Part NumberPIC16LF877-04I/PT
DescriptionIC PIC MCU FLASH 8KX14 44TQFP
ManufacturerMicrochip Technology
SeriesPIC® 16F
PIC16LF877-04I/PT datasheets

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Specifications of PIC16LF877-04I/PT

Core Size8-BitProgram Memory Size14KB (8K x 14)
Core ProcessorPICSpeed4MHz
ConnectivityI²C, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, POR, PWM, WDT
Number Of I /o33Program Memory TypeFLASH
Eeprom Size256 x 8Ram Size368 x 8
Voltage - Supply (vcc/vdd)2 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeExternalOperating Temperature-40°C ~ 85°C
Package / Case44-TQFP, 44-VQFPController Family/seriesPIC16LF
No. Of I/o's33Eeprom Memory Size256Byte
Ram Memory Size368ByteCpu Speed4MHz
No. Of Timers3Lead Free Status / RoHS StatusLead free / RoHS Compliant
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2
9.2.10
I
C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I
module is in the IDLE state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<6:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (T
). When the baud rate generator
BRG
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled high
the baud rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one T
. This action is then
BRG
followed by assertion of the SDA pin (SDA is low) for
one T
, while SCL is high. Following this, the RSEN
BRG
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the baud rate generator has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
• SDA is sampled low when SCL
goes from low to high.
•
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 9-13:
REPEAT START CONDITION WAVEFORM
Write to SSPCON2
occurs here
SDA = 1,
SCL (no change)
SDA
Falling edge of ninth clock
End of Xmit
SCL
2001 Microchip Technology Inc.
PIC16F87X
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
2
C
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
9.2.10.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
Set S (SSPSTAT<3>)
SDA = 1,
At completion of START bit,
SCL = 1
hardware clears RSEN bit
and sets SSPIF
T
T
T
BRG
BRG
BRG
1st bit
Write to SSPBUF occurs here
T
BRG
T
BRG
Sr = Repeated START
DS30292C-page 81

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