AT89C51CC03CA-RLTUM Atmel, AT89C51CC03CA-RLTUM Datasheet - Page 131

IC 8051 MCU 64K FLASH 44-VQFP

AT89C51CC03CA-RLTUM

Manufacturer Part Number
AT89C51CC03CA-RLTUM
Description
IC 8051 MCU 64K FLASH 44-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet

Specifications of AT89C51CC03CA-RLTUM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44VQFP
Device Core
8051
Family Name
AT89
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51CC03CA-RLTUM
Manufacturer:
ADI
Quantity:
141
Part Number:
AT89C51CC03CA-RLTUM
Manufacturer:
Atmel
Quantity:
10 000
Functional Description
Figure 58. SPI Module Block Diagram
Operating Modes
4182O–CAN–09/08
SPSCR
SPCON
SPIF
SPR2
SPEN
-
OVR
SSDIS
SPI
Control
MODF
MSTR
Figure 58 shows a detailed structure of the SPI Module.
The Serial Peripheral Interface can be configured in one of the two modes: Master mode
or Slave mode. The configuration and initialization of the SPI Module is made through
two registers:
Once the SPI is configured, the data exchange is made using:
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
Internal Bus
The Serial Peripheral Control register (SPCON)
The Serial Peripheral Status and Control Register (SPSCR)
The Serial Peripheral DATa register (SPDAT)
SPTE
CPOL CPHA
UARTM SPTEIE MODFIE
SPR1
SPR0
SPDAT
Transmit Data Register
Receive Data Register
PERIPH
FCLK
7
Clock
Logic
Shift Register
6
5
4
3
SPI Interrupt
Request
2
1
0
AT89C51CC03
M
S
Pin
Control
Logic
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS
131

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