AT89C51CC03CA-RLTUM Atmel, AT89C51CC03CA-RLTUM Datasheet - Page 41

IC 8051 MCU 64K FLASH 44-VQFP

AT89C51CC03CA-RLTUM

Manufacturer Part Number
AT89C51CC03CA-RLTUM
Description
IC 8051 MCU 64K FLASH 44-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet

Specifications of AT89C51CC03CA-RLTUM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44VQFP
Device Core
8051
Family Name
AT89
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51CC03CA-RLTUM
Manufacturer:
ADI
Quantity:
141
Part Number:
AT89C51CC03CA-RLTUM
Manufacturer:
Atmel
Quantity:
10 000
External Code Memory Access
Memory Interface
External Bus Cycles
4182O–CAN–09/08
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (PSEN#, and ALE).
Figure 21 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21
describes the external memory interface signals.
Figure 21. External Code Memory Interface Structure
Table 12. External Code Memory Interface Signals
This section describes the bus cycles the AT89C51CC03 executes to fetch code (see
Figure 22) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode see section “Clock “.
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
For bus cycling parameters refer to the ‘AC-DC parameters’ section.
Signal
PSEN#
Name
AD7:0
A15:8
ALE
Type
I/O
O
O
O
Description
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
Program Store Enable Output
This signal is active low during external code fetch or external code read
(MOVC instruction).
AT89C51CC0
PSEN#
ALE
P2
P0
AD7:0
A15:8
Latch
A7:0
A15:8
A7:0
D7:0
OE
EPROM
AT89C51CC03
Flash
Alternate
Function
P2.7:0
P0.7:0
-
-
41

Related parts for AT89C51CC03CA-RLTUM