AT32UC3B0256-Z2UT Atmel, AT32UC3B0256-Z2UT Datasheet

IC MCU AVR32 256KB FLASH 64-QFN

AT32UC3B0256-Z2UT

Manufacturer Part Number
AT32UC3B0256-Z2UT
Description
IC MCU AVR32 256KB FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3B0256-Z2UT

Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFN
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
44
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0256-Z2UT
Manufacturer:
ATMEL
Quantity:
444
Features
High Performance, Low Power AVR
Multi-hierarchy Bus System
Internal High-Speed Flash
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
Interrupt Controller
System Functions
Universal Serial Bus (USB)
One Three-Channel 16-bit Timer/Counter (TC)
One 7-Channel 20-bit Pulse Width Modulation Controller (PWM)
Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
One Synchronous Serial Protocol Controller
One Master/Slave Two-Wire Interface (TWI), 400kbit/s I
One 8-channel 10-bit Analog-To-Digital Converter, 384ks/s
16-bit Stereo Audio Bitstream DAC
QTouch
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing up to 1.39 DMIPS / MHz
– Memory Protection Unit
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 7 Peripheral DMA Channels Improves Speed for Peripheral Communication
– 512K Bytes, 256K Bytes, 128K Bytes, 64K Bytes Versions
– Single Cycle Access up to 30 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
– 96K Bytes (512KB Flash), 32K Bytes (256KB and 128KB Flash), 16K Bytes (64KB
– Autovectored Low Latency Interrupt Service with Programmable Priority
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing
– Watchdog Timer, Real-Time Clock Timer
– Device 2.0 and Embedded Host Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
– USB Wake Up from Sleep Functionality
– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities
– Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
– Supports I
– Sample Rate Up to 50 KHz
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch
Flash)
Independant CPU Frequency from USB Frequency
• Up to 83 DMIPS Running at 60 MHz from Flash
• Up to 46 DMIPS Running at 30 MHz from Flash
®
Library Support
®
and QMatrix
2
S and Generic Frame-Based Protocols
®
Acquisition
®
32 UC 32-Bit Microcontroller
2
C-compatible
32-bit AVR
Microcontroller
AT32UC3B0512
AT32UC3B0256
AT32UC3B0128
AT32UC3B064
AT32UC3B1512
AT32UC3B1256
AT32UC3B1128
AT32UC3B164
Summary
32059K–03/2011
®

Related parts for AT32UC3B0256-Z2UT

AT32UC3B0256-Z2UT Summary of contents

Page 1

... Sample Rate KHz ® • QTouch Library Support – Capacitive Touch Buttons, Sliders, and Wheels ® ® – QTouch and QMatrix Acquisition ® 32-Bit Microcontroller 2 C-compatible ® 32-bit AVR Microcontroller AT32UC3B0512 AT32UC3B0256 AT32UC3B0128 AT32UC3B064 AT32UC3B1512 AT32UC3B1256 AT32UC3B1128 AT32UC3B164 Summary 32059K–03/2011 ...

Page 2

On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins) • 5V Input Tolerant I/Os, including 4 high-drive pins • Single 3.3V ...

Page 3

... End-Point configuration. The Embedded Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers ...

Page 4

Overview 2.1 Blockdiagram Figure 2-1. Block diagram TCK TDO INTERFACE TDI TMS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBUS D+ D- INTERFACE ID VBOF PA PB EXTINT[7..0] KPS[7..0] NMI 115 kHz RCOSC 32 KHz XIN32 XOUT32 OSC XIN0 OSC0 XOUT0 ...

Page 5

... PWM Channels Watchdog Timer Real-Time Clock Timer Power Manager Oscillators 10-bit ADC number of channels JTAG Max Frequency Package 32059K–03/2011 Configuration Summary AT32UC3B0512 AT32UC3B0256/128/64 512 KB 256/128/64 KB 96KB 32/32/16KB 44 8 Mini-Host + Device PLL 80-240 MHz (PLL0/PLL1) Crystal Oscillators 0.4-20 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 115 kHz (RCSYS) Crystal Oscillators 0 ...

Page 6

Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi- plexing on I/O Line section. Figure 4-1. VDDPLL VDDCORE RESET_N 32059K–03/2011 TQFP64 / QFN64 Pinout GND ...

Page 7

Figure 4-2. Note: 4.2 Peripheral Multiplexing on I/O lines 4.2.1 Multiplexed signals Each GPIO line can be assigned to one of 4 peripheral functions only avail- able for UC3Bx512 parts). The following table ...

Page 8

Table 4-1. GPIO Controller Function Multiplexing 11 13 PA07 GPIO PA08 GPIO PA09 GPIO PA10 GPIO PA11 GPIO PA12 GPIO PA13 GPIO ...

Page 9

Table 4-1. GPIO Controller Function Multiplexing 55 PB09 GPIO 41 57 PB10 GPIO 42 58 PB11 GPIO 43 4.2.2 JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the ...

Page 10

Table 4-4. QFP48 pin 4.3 High Drive Current GPIO Ones of GPIOs can be used to drive twice current than other GPIO capability (see Electrical Characteristics section). Table 4-5. 5. Signals Description The following table gives details on the signal ...

Page 11

Table 5-1. Signal Description List (Continued) Signal Name Function VDDOUT Voltage Regulator Output GNDANA Analog Ground GND Ground XIN0, XIN1, XIN32 Crystal Input XOUT0, XOUT1, Crystal Output XOUT32 TCK Test Clock TDI Test Data ...

Page 12

Table 5-1. Signal Description List (Continued) Signal Name Function MISO Master In Slave Out MOSI Master Out Slave In NPCS0 - NPCS3 SPI Peripheral Chip Select SCK Clock RX_CLOCK SSC Receive Clock RX_DATA SSC Receive Data RX_FRAME_SYNC SSC Receive Frame ...

Page 13

Table 5-1. Signal Description List (Continued) Signal Name Function DCD Data Carrier Detect DSR Data Set Ready DTR Data Terminal Ready RI Ring Indicator RTS Request To Send RXD Receive Data TXD Transmit Data AD0 - AD7 Analog input pins ...

Page 14

RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system ...

Page 15

Figure 5-1. 3.3V 5.6.2 Voltage Regulator 5.6.2.1 Single Power Supply The AT32UC3B embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT that should be ...

Page 16

Refer to For decoupling recommendations for VDDIO, VDDANA, VDDCORE and VDDPLL, please refer to the Schematic checklist. 5.6.2.2 Dual Power Supply In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current. ...

Page 17

Processor and Architecture Rev: 1.0.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...

Page 18

The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some ...

Page 19

Figure 6-1. 6.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one ...

Page 20

Figure 6-2. 6.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...

Page 21

The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 6-1. Instruction ld.d st.d 6.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if ...

Page 22

Programming Model 6.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 6-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...

Page 23

Figure 6-5. Bit 6.4.3 Processor States 6.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in page 23. Table 6-2. Priority N/A N/A Mode ...

Page 24

All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described ...

Page 25

Table 6-3. Reg # 33- ...

Page 26

Table 6-3. Reg # 100 101 102 103-191 192-255 6.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have ...

Page 27

The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter ...

Page 28

Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated ...

Page 29

Table 6-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x8000_0000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...

Page 30

Module Configuration All AT32UC3B parts do not implement the same CPU and Architecture Revision. Table 6-5. Part Name AT32UC3Bx512 AT32UC3Bx256 AT32UC3Bx128 AT32UC3Bx64 32059K–03/2011 CPU and Architecture Revision Architecture Revision AT32UC3B 30 ...

Page 31

... KBytes (AT32UC3B064, AT32UC3B164) • Internal High-Speed SRAM, Single-cycle access at full speed – 96KBytes ((AT32UC3B0512, AT32UC3B1512) – 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128) – 16KBytes (AT32UC3B064 and AT32UC3B164) 7.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...

Page 32

Peripheral Address Map Table 7-2. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFF0000 0xFFFF0800 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2400 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 32059K–03/2011 Peripheral Name USB USB 2.0 Interface - USB HMATRIX HSB Matrix ...

Page 33

Table 7-2. Peripheral Address Mapping 0xFFFF3C00 0xFFFF4000 7.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore ...

Page 34

Boot Sequence This chapter summarizes the boot sequence of the AT32UC3B. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to section Power Manager (PM). 8.1 Starting of clocks After power-up, the device will ...

Page 35

Electrical Characteristics 9.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on GPIO Pins with respect to Ground for TCK, RESET_N, PA03, PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, PA19, PA28, ...

Page 36

... All I/O pins except TCK, RESET_N, PA03, PA04, AT32UC3B064 PA05, PA06, PA07, PA08, AT32UC3B0128 PA11, PA12, PA18, PA19, PA28, PA29, PA30, PA31 AT32UC3B0256 AT32UC3B164 TCK, RESET_N, PA03, AT32UC3B1128 PA04, PA05, PA06, PA07, PA08, PA11, PA12, PA18, AT32UC3B1256 PA19, PA28, PA29, PA30, ...

Page 37

... PA21, PA22, PA23, RESET_N, TCK, TDI, AT32UC3B0512 TMS pins AT32UC3B1512 PA20, PA21, PA22, PA23 RESET_N pin, TCK, TDI, TMS pins VDDCORE AT32UC3B064 1.8V, AT32UC3B0128 device in static AT32UC3B0256 mode AT32UC3B164 All inputs driven AT32UC3B1128 including JTAG; AT32UC3B1256 RESET_N VDDCORE 1.8V, device in static AT32UC3B0512 mode ...

Page 38

Regulator Characteristics Table 9-2. Electrical Characteristics Symbol Parameter V Supply voltage (input) VDDIN V Supply voltage (output) VDDOUT I Maximum DC output current OUT I Static Current of internal regulator SCR Table 9-3. Decoupling Requirements Symbol Parameter C Input ...

Page 39

Table 9-7. BOD Timing Symbol Parameter Minimum time with VDDCORE < T BOD VBOD to detect power failure 9.4.3 Reset Sequence Table 9-8. Electrical Characteristics Symbol Parameter VDDCORE rise rate to ensure power- V DDRR on-reset VDDCORE fall rate to ...

Page 40

Figure 9-1. VDDCORE RESET_N Internal POR Reset Internal MCU Reset Figure 9-2. VDDCORE RESET_N Internal POR Reset Internal MCU Reset Figure 9-3. VDDCORE RESET_N BOD Reset WDT Reset Internal MCU Reset In dual supply configuration, the power up sequence must ...

Page 41

Therefore VDDCORE rise rate (VDDRR) must be equal or superior to 2.5V/ms and VDDIO must reach VDDIO mini value before 500 us (< TRST + TSSU1) after VDDCORE has reached V min value. Figure 9- ...

Page 42

Power Consumption The values in ues of power consumption with operating conditions as follows: •V DDIO •V DDCORE •T = 25° •I/Os are configured in input, pull-up enabled. Figure 9-5. The following tables represent the power consumption ...

Page 43

... Power Consumtion for Different Sleep Modes Table 9-10. Power Consumption for Different Sleep Modes for AT32UC3B064, AT32UC3B0128, AT32UC3B0256, AT32UC3B164, AT32UC3B1128, AT32UC3B1256 Mode Conditions - CPU running a recursive Fibonacci Algorithm from flash and clocked from PLL0 at f MHz. - Voltage regulator is on. - XIN0: external clock. Xin1 Stopped. XIN32 stopped. ...

Page 44

... ABDAC 32059K–03/2011 Typ. 0.0537xf(MHz)+0.166 3 Voltage Regulator On 15.5 Voltage Regulator Off 7.5 < 160 MHz and 10 MHz < f PLL0 Conditions Consumption AT32UC3B064 AT32UC3B0128 AT32UC3B0256 AT32UC3B164 AT32UC3B1128 AT32UC3B1256 AT32UC3B0512 AT32UC3B1512 AT32UC3B0512 AT32UC3B1512 AT32UC3B Unit mA/MHz mA µA µA µA < 12 MHz. XIN0 Unit ...

Page 45

System Clock Characteristics These parameters are given in the following conditions: • V DDCORE • Ambient Temperature = 25°C 9.6.1 CPU/HSB Clock Characteristics Table 9-13. Core Clock Waveform Parameters Symbol Parameter 1/(t ) CPU Clock Frequency CPCPU t CPU ...

Page 46

Oscillator Characteristics The following characteristics are applicable to the operating temperature range: T power supply, unless otherwise specified. 9.7.1 Slow Clock RC Oscillator Table 9-16. RC Oscillator Frequency Symbol Parameter F RC Oscillator Frequency RC 9.7.2 32 KHz Oscillator ...

Page 47

Main Oscillators Table 9-18. Main Oscillators Characteristics Symbol Parameter 1/(t ) Oscillator Frequency CPMAIN Internal Load Capacitance ( ESR Crystal Equivalent Series Resistance Duty Cycle t Startup Time ST t XIN Clock High Half-period ...

Page 48

ADC Characteristics Table 9-20. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Track and Hold Input Resistor Track and Hold Capacitor Conversion Time Throughput Rate Notes: 1. ...

Page 49

Table 9-23. Transfer Characteristics in 8-bit Mode Parameter Differential Non-linearity Offset Error Gain Error Table 9-24. Transfer Characteristics in 10-bit Mode Parameter Resolution Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error 32059K–03/2011 Conditions ADC Clock = 5 MHz ...

Page 50

USB Transceiver Characteristics 9.9.1 Electrical Characteristics Table 9-25. Electrical Parameters Symbol Parameter Recommended external USB series R EXT resistor The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers ...

Page 51

JTAG Characteristics 9.10.1 JTAG Timing Figure 9-6. TMS/TDI Boundary Scan Inputs Boundary Scan Outputs (1) Table 9-26. JTAG Timings Symbol Parameter JTAG0 TCK Low Half-period JTAG1 TCK High Half-period JTAG2 TCK Period JTAG3 TDI, TMS Setup before TCK High ...

Page 52

SPI Characteristics Figure 9-7. SPCK MISO MOSI Figure 9-8. SPCK MISO MOSI Figure 9-9. SPCK MISO MOSI 32059K–03/2011 SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPI 0 SPI 2 SPI Master mode with ...

Page 53

Figure 9-10. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK MISO MOSI Table 9-27. SPI Timings Symbol Parameter MISO Setup time before SPCK rises SPI 0 (master) MISO Hold time after SPCK rises SPI ...

Page 54

Flash Memory Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Flash operating frequency ...

Page 55

Mechanical Characteristics 10.1 Thermal Considerations 10.1.1 Thermal Data Table 10-1 Table 10-1. Symbol θ JA θ JC θ JA θ JC 10.1.2 Junction Temperature The average chip-junction temperature where: • θ = package thermal ...

Page 56

Package Drawings Figure 10-1. TQFP-64 package drawing Table 10-2. Device and Package Maximum Weight Weight Table 10-3. Package Characteristics Moisture Sensitivity Level Table 10-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32059K–03/2011 300 mg Jedec J-STD-20D-MSL3 MS-026 e3 AT32UC3B ...

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Figure 10-2. TQFP-48 package drawing Table 10-5. Device and Package Maximum Weight Weight Table 10-6. Package Characteristics Moisture Sensitivity Level Table 10-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32059K–03/2011 100 mg Jedec J-STD-20D-MSL3 MS-026 e3 AT32UC3B 57 ...

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Figure 10-3. QFN-64 package drawing Table 10-8. Device and Package Maximum Weight Weight Table 10-9. Package Characteristics Moisture Sensitivity Level Table 10-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32059K–03/2011 200 mg Jedec J-STD-20D-MSL3 M0-220 e3 AT32UC3B 58 ...

Page 59

Figure 10-4. QFN-48 package drawing Table 10-11. Device and Package Maximum Weight Weight Table 10-12. Package Characteristics Moisture Sensitivity Level Table 10-13. Package Reference JEDEC Drawing Reference JESD97 Classification 32059K–03/2011 100 mg Jedec J-STD-20D-MSL3 M0-220 e3 AT32UC3B 59 ...

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Soldering Profile Table 10-14 Table 10-14. Soldering Profile Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5⋅C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25⋅C to ...

Page 61

... Ordering Information Device Ordering Code AT32UC3B0512 AT32UC3B0512-A2UES AT32UC3B0512-A2UR AT32UC3B0512-A2UT AT32UC3B0512-Z2UES AT32UC3B0512-Z2UR AT32UC3B0512-Z2UT AT32UC3B0256 AT32UC3B0256-A2UT AT32UC3B0256-A2UR AT32UC3B0256-Z2UT AT32UC3B0256-Z2UR AT32UC3B0128 AT32UC3B0128-A2UT AT32UC3B0128-A2UR AT32UC3B0128-Z2UT AT32UC3B0128-Z2UR AT32UC3B064 AT32UC3B064-A2UT AT32UC3B064-A2UR AT32UC3B064-Z2UT AT32UC3B064-Z2UR AT32UC3B1512 AT32UC3B1512-Z1UT AT32UC3B1512-Z1UR AT32UC3B1256 AT32UC3B1256-AUT AT32UC3B1256-AUR AT32UC3B1256-Z1UT AT32UC3B1256-Z1UR AT32UC3B1128 AT32UC3B1128-AUT AT32UC3B1128-AUR AT32UC3B1128-Z1UT AT32UC3B1128-Z1UR AT32UC3B164 ...

Page 62

Errata 12.1 AT32UC3B0512, AT32UC3B1512 12.1.1 Rev D - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned ...

Page 63

SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround ...

Page 64

This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where the system RC oscillator is stopped, make sure that the factor between the CPU/HSB and ...

Page 65

USB 1. UPCFGn.INTFRQ is irrelevant for isochronous pipe As a consequence, isochronous IN and OUT tokens are sent every 1 ms (Full Speed), or every 125 uS (High Speed). Fix/Workaround ForHigher polling time, the software must freeze the pipe ...

Page 66

TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 ...

Page 67

In the interrupt handler code, write a one to the RTSDIS bit in the USART Control Register (CR). This will drive the RTS output high. After the next DMA trans- fer is started and a ...

Page 68

Rev C - PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...

Page 69

SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a Software Reset. 5. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and ...

Page 70

Increased Power Consunption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis- abled, this will lead to an increased power consumption in VDDIO. Fix/Workaround Disable ...

Page 71

PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID Wrong PDCA behavior when using two PDCA channels with the same PID. Fix/Workaround The same PID should not be assigned to more than one channel. ...

Page 72

Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer ...

Page 73

RTSEN bit in the USART CR so that RTS will be driven low. 4. Corruption after receiving too many bits in SPI slave mode If the ...

Page 74

... AT32UC3B0256, AT32UC3B0128, AT32UC3B064, AT32UC3B1256, AT32UC3B1128, AT32UC3B164 All industrial parts labelled with -UES (for engineering samples) are revision B parts. 12.2.1 Rev PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. ...

Page 75

Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now befin and RXREADY will now behave as expected. 4. SPI disable does not work in SLAVE mode SPI disable does not work in ...

Page 76

SSC 1. Additional delay on TD output A delay from system clock cycles is added to TD output when: TCMR.START = Receive Start, TCMR.STTDLY = more than ZERO, RCMR.START = Start on falling edge / Start ...

Page 77

Transfer error will stall a transmit peripheral handshake interface If a tranfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more ...

Page 78

Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer ...

Page 79

USART has been disabled, reseted by a soft reset and re-enabled. Fix/Workaround None. 5. USART slave synchronous mode external clock must be at least 9 times lower in fre- quency than CLK_USART ...

Page 80

Rev PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...

Page 81

SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a Software Reset. 5. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and ...

Page 82

SSC 1. Additional delay on TD output A delay from system clock cycles is added to TD output when: TCMR.START = Receive Start, TCMR.STTDLY = more than ZERO, RCMR.START = Start on falling edge / Start ...

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Transfer error will stall a transmit peripheral handshake interface If a tranfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more ...

Page 84

OCD 1. The auxiliary trace does not work for CPU/HSB speed higher than 50MHz The auxiliary trace does not work for CPU/HSB speed higher than 50MHz. Fix/Workaround Do not use the auxiliary trace for CPU/HSB speed higher than 50MHz. ...

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The RTS output does not function correctly in hardware handshaking mode The RTS signal is not generated properly when the USART receives data in hardware hand- shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output ...

Page 86

DSP Operations 1. Instruction breakpoints affected on all MAC instruction Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 32059K–03/2011 AT32UC3B 86 ...

Page 87

Rev PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...

Page 88

SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a Software Reset. 5. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and ...

Page 89

SSC 1. Additional delay on TD output A delay from system clock cycles is added to TD output when: TCMR.START = Receive Start, TCMR.STTDLY = more than ZERO, RCMR.START = Start on falling edge / Start ...

Page 90

Transfer error will stall a transmit peripheral handshake interface If a tranfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more ...

Page 91

SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. - OCD 1. The auxiliary trace does not work for CPU/HSB speed higher than 50MHz The auxiliary trace does not work for CPU/HSB speed ...

Page 92

ISO7816 Mode T1: RX impossible after any TX RX impossible after any TX. Fix/Workaround SOFT_RESET on RX+ Config US_MR + Config_US_CR. 3. The RTS output does not function correctly in hardware handshaking mode The RTS signal is not generated ...

Page 93

It is then safe to read and fetch code from the flash. - DSP Operations 1. Instruction breakpoints affected on all MAC instruction Hardware ...

Page 94

Rev PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and ...

Page 95

SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround ...

Page 96

USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.RESET bit may not been cleared ...

Page 97

USART RXBREAK problem when no timeguard In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. Fix/Workaround If the NBSTOP is 1, timeguard ...

Page 98

PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0] on revision B instead of WriteData[7:0], ByteAddress[2:0] PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0] on revision B instead of WriteData[7:0], ByteAddress[2:0]. Fix/Workaround None. 4. ...

Page 99

Processor and Architecture 1. Local Busto fast GPIO not available on silicon Rev B Local bus is only available for silicon RevE and later. Fix/Workaround Do not use if silicon revison older than F. 2. Memory Protection Unit (MPU) ...

Page 100

SR mode will indicate an exception. A RETE instruction would then corrupt the stack. Fix/Workaround Follow the rules of the AVR32UC Technical Reference Manual. To increase software robustness, if ...

Page 101

Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 13.1 Rev. K– 02/2011 13.2 ...

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Rev. F – 04/2008 1. 13.7 Rev. E – 12/2007 1. 13.8 Rev. D – 11/2007 1. 2. 13.9 Rev. C – 10/2007 13.10 Rev. B – 07/2007 1. 2. ...

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Table of Contents 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 4 3 Configuration Summary .......................................................................... 5 4 Package and Pinout ................................................................................. 6 5 Signals Description ............................................................................... 10 6 Processor and Architecture .................................................................. 17 7 Memories ................................................................................................ 31 8 Boot Sequence ...

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... Flash Memory Characteristics .........................................................................54 10.1 Thermal Considerations ..................................................................................55 10.2 Package Drawings ...........................................................................................56 10.3 Soldering Profile ..............................................................................................60 12.1 AT32UC3B0512, AT32UC3B1512 ..................................................................62 12.2 AT32UC3B0256, AT32UC3B0128, AT32UC3B064, AT32UC3B1256, AT32UC3B1128, AT32UC3B164 74 13.1 Rev. K– 02/2011 ............................................................................................101 13.2 Rev. J– 12/2010 ............................................................................................101 13.3 Rev. I – 06/2010 ............................................................................................101 13.4 Rev. H – 10/2009 ...........................................................................................101 13.5 Rev. G – ...

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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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