AT90USB1287-AU Atmel, AT90USB1287-AU Datasheet

IC AVR MCU 128K 64TQFP

AT90USB1287-AU

Manufacturer Part Number
AT90USB1287-AU
Description
IC AVR MCU 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheets

Specifications of AT90USB1287-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT90USBx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR USB
No. Of I/o's
48
Eeprom Memory Size
4KB
Ram Memory Size
8KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT90USB1287-16AU
AT90USB1287-16AU

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Price
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ATMEL
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AT90USB1287-AU
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Atmel
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AT90USB1287-AUR
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Atmel
Quantity:
10 000
Features
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
JTAG (IEEE std. 1149.1 compliant) Interface
USB 2.0 Full-speed/Low-speed Device and On-The-Go Module
USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
USB OTG Reduced Host :
Peripheral Features
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
– 64/128K Bytes of In-System Self-Programmable Flash
– Optional Boot Code Section with Independent Lock Bits
– 2K/4K (64K/128K Flash version) Bytes EEPROM
– 4K/8K (64K/128K Flash version) Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Complies fully with:
– Universal Serial Bus Specification REV 2.0
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s
– Endpoint 0 for Control Transfers : up to 64-bytes
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independant 832 bytes USB DPRAM for endpoint memory allocation
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz PLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
– Provide Status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
Isochronous Transfers
for OTG dual-role devices
• Endurance: 100,000 Write/Erase Cycles
• USB Bootloader programmed by default in the Factory
• In-System Programming by On-chip Boot Program hardware activated after
• True Read-While-Write Operation
• All supplied parts are preprogramed with a default USB bootloader
• Endurance: 100,000 Write/Erase Cycles
reset
®
8-Bit Microcontroller
8-bit
Microcontroller
with
64/128K Bytes
of ISP Flash
and USB
Controller
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287
7593K–AVR–11/09

Related parts for AT90USB1287-AU

AT90USB1287-AU Summary of contents

Page 1

... Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode ® 8-Bit Microcontroller 8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 7593K–AVR–11/09 ...

Page 2

Real Time Counter with Separate Oscillator – Four 8-bit PWM Channels – Six PWM Channels with Programmable Resolution from Bits – Output Compare Modulator – 8-channels, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial ...

Page 3

Pin Configurations Figure 1-1. 1 (INT.6/AIN.0) PE6 2 (INT.7/AIN.1/UVcon) PE7 3 UVcc UGnd 7 UCap 8 VBus 9 (IUID) PE3 10 (SS/PCINT0) PB0 11 (PCINT1/SCLK) PB1 12 (PDI/PCINT2/MOSI) PB2 13 (PDO/PCINT3/MISO) PB3 14 (PCINT4/OC.2A) ...

Page 4

Figure 1-2. (INT.6/AIN.0) PE6 (INT.7/AIN.1/UVcon) PE7 (SS/PCINT0) PB0 (PCINT1/SCLK) PB1 (PDI/PCINT2/MOSI) PB2 (PDO/PCINT3/MISO) PB3 (PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PB5 (PCINT6/OC.1B) PB6 Note: 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured ...

Page 5

AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PF7 - PF0 VCC POR TF DRIVERS GND DATA REGISTER PORT F AVCC ADC ...

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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90USB64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90USB64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits ...

Page 7

Pin Descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 AVCC Analog supply voltage. 2.2.4 Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output ...

Page 8

Port E (PE7..PE0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E ...

Page 9

XTAL2 Output from the inverting Oscillator amplifier. 2.2.19 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 2.2.20 AREF This is the ...

Page 10

AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...

Page 11

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...

Page 12

Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...

Page 13

Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 4.5 General Purpose Register File The Register File is optimized for the ...

Page 14

Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.6 Stack Pointer The Stack is mainly used for storing ...

Page 15

Extended Z-pointer Register for ELPM/SPM - RAMPZ Bit Read/Write Initial Value For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4. Note that LPM is not affected by the RAMPZ setting. ...

Page 16

Figure 4-6. Register Operands Fetch ALU Operation Execute 4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts ...

Page 17

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be ...

Page 18

Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: ...

Page 19

AVR AT90USB64/128 Memories This section describes the different memories in the AT90USB64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90USB64/128 features an EEPROM Memory for data storage. ...

Page 20

The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Programming” on page 366 using the SPI pins or the JTAG interface. Constant tables can be allocated within the ...

Page 21

An optional external data SRAM can be used with the AT90USB64/128. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, ...

Page 22

Figure 5-2. 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk AT90USB64/128 22 Data Memory Map D ata M emory 32 R ...

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Figure 5-3. 5.3 EEPROM Data Memory The AT90USB64/128 contains 2K/4K bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at ...

Page 24

The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value • Bits 15..12 – Res: Reserved Bits These bits are reserved bits in the AT90USB64/128 and will always read as zero. • Bits 11..0 – EEAR8..0: EEPROM ...

Page 25

Table 5-2. EEPM1 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. ...

Page 26

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is ...

Page 27

Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData Note: 7593K–AVR–11/09 (1) ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, ...

Page 28

The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...

Page 29

I/O Memory The I/O space definition of the AT90USB64/128 is shown in All AT90USB64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...

Page 30

External Memory Interface With all the features the External Memory Interface provides well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD- display, A/D, and D/A. ...

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When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section ...

Page 32

Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode recommended to disable the pull-ups by writing the Port ...

Page 33

Figure 5-7. System Clock (CLK Note: Figure 5-8. System Clock (CLK Note: 7593K–AVR–11/09 External Data Memory Cycles with SRWn1 = 0 and SRWn0 = CPU ALE A15:8 Prev. addr. DA7:0 Prev. data Address WR DA7:0 (XMBK = ...

Page 34

Figure 5-9. System Clock (CLK DA7:0 (XMBK = 0) DA7:0 (XMBK = 1) Note: 5.5.6 External Memory Control Register A – XMCRA Bit Read/Write Initial Value • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE to one enables the ...

Page 35

Table 5-4. SRL2 • Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter- nal ...

Page 36

XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one. • Bit 6..3 – Res: Reserved Bits These bits are reserved and will always read as zero. When writing to ...

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Figure 5-10. Address Map with 32 KB External Memory 5.5.9 Using all 64KB Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in 56KB of External Memory is available by default (address space ...

Page 38

Assembly Code Example ; OFFSET is defined to 0x4000 to ensure ; external memory access ; Configure Port C (address high byte output 0x00 when the pins are released ; for normal Port Pin operation ldi out ldi ...

Page 39

System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

Page 40

Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...

Page 41

Table 6-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual ...

Page 42

Figure 6-2. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3. Frequency Range Notes: The CKSEL0 Fuse ...

Page 43

Table 6-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: Table 6-5. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 6.4 Low Frequency Crystal Oscillator ...

Page 44

Note: 6.5 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nom- inal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock ...

Page 45

Table 6-8. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 6.5.1 Oscillator Calibration Register – OSCCAL Bit Read/Write Initial Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the ...

Page 46

Figure 6-3. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-9. Table 6-9. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock ...

Page 47

System Clock Prescaler The AT90USB64/128 has a system clock prescaler, and the system clock can be divided by set- ting the the system clock frequency and the power consumption when the requirement for processing power is low. This can ...

Page 48

This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any ...

Page 49

Figure 6-4. XTAL1 XTAL2 6.10.2 PLL Control and Status Register – PLLCSR Bit $29 ($29) Read/Write Initial Value • Bit 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90USB64/128 and always read as zero. • Bit ...

Page 50

Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started. • Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock. After the ...

Page 51

Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...

Page 52

Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt ...

Page 53

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt ...

Page 54

Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher- als to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read ...

Page 55

Read/Write Initial Value • Bit 7 - PRUSB: Power Reduction USB Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When waking up the USB again, the USB should be re ...

Page 56

Refer to on how to configure the Brown-out Detector. 7.8.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these ...

Page 57

System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...

Page 58

Figure 8-1. BODLEVEL [2..0] Table 8-1. Symbol V POT V POR V CCRR V RST t RST Notes: 8.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR ...

Page 59

RESET after V rise. The RESET signal is activated again, without any delay, when V CC the detection level. Figure 8-2. TIME-OUT INTERNAL Figure 8-3. TIME-OUT ...

Page 60

Figure 8-4. 8.5 Brown-out Detection AT90USB64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. ...

Page 61

Figure 8-5. 8.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 63 ...

Page 62

Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 1 – EXTRF: External ...

Page 63

Watchdog Timer AT90USB64/128 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms ...

Page 64

In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...

Page 65

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...

Page 66

Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling ...

Page 67

Table 8-6. WDP3 7593K–AVR–11/09 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles 0 0 ...

Page 68

Interrupts This section describes the specifics of the interrupt handling as performed in AT90USB64/128. For a general explanation of the AVR interrupt handling, refer to on page 9.1 Interrupt Vectors in AT90USB64/128 Table 9-1. Vector No ...

Page 69

Table 9-1. Vector No Notes: Table 9-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can ...

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Table 9-2. BOOTRST Note: 9.1.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 9.1.2 MCU Control Register – MCUCR Bit Read/Write Initial Value • ...

Page 71

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as ...

Page 72

I/O-Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...

Page 73

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...

Page 74

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...

Page 75

Figure 10-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...

Page 76

Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out ; Insert nop for synchronization nop ; Read port pins in ... C Code Example unsigned char i; ... ...

Page 77

Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable ...

Page 78

Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...

Page 79

MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...

Page 80

Note: Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 10.3.3 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 10-6. Port Pin PB7 PB6 PB5 PB4 PB3 ...

Page 81

OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC1C pin ...

Page 82

PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source. • SS/PCINT0 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured ...

Page 83

Alternate Functions of Port C The Port C alternate function is as follows: Table 10-9. Table 10-10 shown in Table 10-10. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...

Page 84

Table 10-11. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 10.3.5 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 10-12. Port ...

Page 85

ICP1 – Port D, Bit 4 ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1. • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3: The PD3 pin ...

Page 86

Table 10-13. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 10-14. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...

Page 87

Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 10-15. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • INT7/AIN.1/UVCON – Port E, Bit 7 ...

Page 88

ALE is the external data memory Address latch enable. HWB allows to execute the bootloader section after reset when tied to ground during external reset pulse. The HWB mode of this pin is active only when the HWBE fuse is ...

Page 89

Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in some Port F pins are configured as outputs essential that these do not switch when a ...

Page 90

Analog to Digital Converter, Channel 3..0. Table 10-19. Overriding Signals for Alternate Functions in PF7..PF4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 10-20. Overriding Signals for Alternate Functions in PF3..PF0 Signal Name PUOE PUOV ...

Page 91

Port A Data Direction Register – DDRA Bit Read/Write Initial Value 10.4.3 Port A Input Pins Address – PINA Bit Read/Write Initial Value 10.4.4 Port B Data Register – PORTB Bit Read/Write Initial Value 10.4.5 Port B Data Direction ...

Page 92

Port D Data Register – PORTD Bit Read/Write Initial Value 10.4.11 Port D Data Direction Register – DDRD Bit Read/Write Initial Value 10.4.12 Port D Input Pins Address – PIND Bit Read/Write Initial Value 10.4.13 Port E Data Register ...

Page 93

Port F Input Pins Address – PINF Bit Read/Write Initial Value 7593K–AVR–11/ PINF7 PINF6 PINF5 PINF4 R/W R/W R/W R/W N/A N/A N/A N/A AT90USB64/128 PINF3 PINF2 PINF1 PINF0 R/W R/W ...

Page 94

External Interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT7..0 pins are configured as outputs. This feature provides ...

Page 95

Table 11-1. ISCn1 Note: Table 11-2. Symbol t INT 11.0.2 External Interrupt Control Register B – EICRB Bit Read/Write Initial Value • Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt Sense ...

Page 96

Read/Write Initial Value • Bits 7..0 – INT7 – INT0: External Interrupt Request Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding ...

Page 97

Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. 11.0.7 Pin Change Mask Register 0 – PCMSK0 Bit Read/Write Initial Value • ...

Page 98

Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters used as a general name ...

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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f sampling, the maximum ...

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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • ...

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The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen- erator to generate a PWM or variable frequency output on ...

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Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer ...

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Figure 13-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...

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Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...

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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...

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Figure 13-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 13-6. Fast PWM ...

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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 13.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...

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OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See be visible on the port pin if the data direction for the port pin ...

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Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 13-10 mode and PWM mode, where OCR0A is TOP. Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk I/O TCNTn ...

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Initial Value • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of ...

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Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the ...

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Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90USB64/128 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B ...

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A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. • Bit 6 – FOC0B: Force Output Compare B The FOC0B ...

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The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter ...

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Timer/Counter 0 Interrupt Flag Register – TIFR0 Bit Read/Write Initial Value • Bits 7..3, 0 – Res: Reserved Bits These bits are reserved bits in the AT90USB64/128 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter ...

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Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Three independent Output Compare ...

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Figure 14-1. 16-bit Timer/Counter Block Diagram Note: 14.1.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...

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See “Output Compare Units” on page Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the ...

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Assembly Code Examples ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples unsigned int i; ... /* Set TCNTn to 0x01FF */ ...

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TIM16_ReadTCNTn: C Code Example unsigned int TIM16_ReadTCNTn( void ) { } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. The following code examples show how atomic write of the TCNTn Register ...

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TIM16_WriteTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNTn to r17:r16 out TCNTnH,r17 out TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example void TIM16_WriteTCNTn( unsigned int unsigned ...

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Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con- taining the upper eight bits of the counter, and ...

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Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ...

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The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGMn3:0) bits must be set before the TOP ...

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Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is ...

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PWM pulses, thereby making the out- put glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer ...

Page 128

Secondly the COMnx1:0 bits control the OCnx pin output source. schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the ...

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A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 14.8 Modes ...

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Figure 14-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define ...

Page 131

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max- imum resolution is 16-bit ...

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When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next ...

Page 133

OCRnA set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...

Page 134

Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is ...

Page 135

OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...

Page 136

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...

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Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 14-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...

Page 138

Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICF n as TOP) OCRnx (Update at TOP) 14.10 16-bit Timer/Counter Register Description 14.10.1 Timer/Counter1 Control Register A ...

Page 139

When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). 7593K–AVR–11/09 AT90USB64/128 Table ...

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Table 14-1. COMnA1/COMnB1/ COMnC1 Table 14-2 PWM mode. Table 14-2. COMnA1/COMnB1/ COMnC0 Note: Table 14-3 correct and frequency correct PWM mode. AT90USB64/128 140 Compare Output Mode, non-PWM COMnA0/COMnB0/ COMnC0 shows the ...

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Table 14-3. COMnA1/COMnB/ COMnC1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and ...

Page 142

Table 14-4. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...

Page 143

This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit ...

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Table 14-5. CSn2 external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature ...

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Read/Write Initial Value 14.10.8 Timer/Counter3 – TCNT3H and TCNT3L Bit Read/Write Initial Value The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ...

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Output Compare Register 3 B – OCR3BH and OCR3BL Bit Read/Write Initial Value 14.10.14 Output Compare Register 3 C – OCR3CH and OCR3CL Bit Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared ...

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Timer/Counter3 Interrupt Mask Register – TIMSK3 Bit Read/Write Initial Value • Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), ...

Page 148

This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the WGMn3 used as the TOP value, the ICFn Flag is set when the coun- ter ...

Page 149

Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width ...

Page 150

Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...

Page 151

Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...

Page 152

Figure 15-3. Output Compare Unit, Block Diagram The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...

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The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in ...

Page 154

Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x Register ...

Page 155

Figure 15-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

Page 156

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for ...

Page 157

OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 15.6.4 Phase Correct PWM Mode ...

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COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction for ...

Page 159

Figure 15-9 Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 15-10 Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 15-11 7593K–AVR–11/09 shows the same timing data, ...

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Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 15.8 8-bit Timer/Counter Register Description 15.8.1 Timer/Counter Control Register A – TCCR2A Bit Read/Write Initial Value • Bits 7:6 – ...

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Table 15-2 mode. Table 15-2. COM2A1 Note: Table 15-3 rect PWM mode. Table 15-3. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare ...

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Table 15-5 mode. Table 15-5. COM2B1 Note: Table 15-6 rect PWM mode. Table 15-6. COM2B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90USB64/128 ...

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Table 15-7. Mode Notes: 15.8.2 Timer/Counter Control Register B – TCCR2B Bit Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify ...

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Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 15-8. Table 15-8. CS22 ...

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Asynchronous operation of the Timer/Counter 15.9.1 Asynchronous Status Register – ASSR Bit Read/Write Initial Value • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input ...

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The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 15.9.2 Asynchronous Operation ...

Page 167

Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or ...

Page 168

Timer/Counter2 Interrupt Flag Register – TIFR2 Bit Read/Write Initial Value • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B ...

Page 169

The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port ...

Page 170

Output Compare Modulator (OCM1C0A) 16.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare ...

Page 171

When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 16.2.1 Timing Example Figure ...

Page 172

Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ...

Page 173

Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas- ter to Slave on the Master Out ...

Page 174

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 17-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...

Page 175

Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 7593K–AVR–11/09 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock ...

Page 176

The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ...

Page 177

Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the ...

Page 178

SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. ...

Page 179

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled input and is driven low when the SPI is in ...

Page 180

Table 17-5. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 17-3. SPI Transfer Format with CPHA = 0 Figure 17-4. SPI Transfer Format with CPHA = 1 AT90USB64/128 180 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) ...

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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master ...

Page 182

Figure 18-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...

Page 183

XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 18-2 Figure 18-2. Clock Generation Logic, Block Diagram Signal description: txclk ...

Page 184

Table 18-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 18-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f ...

Page 185

External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...

Page 186

A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted ...

Page 187

USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...

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Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by ...

Page 189

For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } ...

Page 190

UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit ...

Page 191

UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: ...

Page 192

Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer error, return -1 andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn) breq USART_ReceiveNoError ldi ldi ...

Page 193

The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not ...

Page 194

The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...

Page 195

Figure 18-5. Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 ...

Page 196

Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop ...

Page 197

Table 18-2. # (Data+Parity Bit) Table 18-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...

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When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit ...

Page 199

UDRn Register location. Reading the UDRn Register location will return the contents of the Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits ...

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This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. • Bit 2 – UPEn: USART Parity Error This bit is set if the ...

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