AT91SAM7X512-CU Atmel, AT91SAM7X512-CU Datasheet
AT91SAM7X512-CU
Specifications of AT91SAM7X512-CU
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AT91SAM7X512-CU Summary of contents
Page 1
... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) • ...
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... VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector • Fully Static Operation MHz at 1.65V and 85° C Worst Case Conditions • Available in 100-lead LQFP Green and 100-ball TFBGA Green Packages AT91SAM7X512/256/128 Preliminary 2 ® Infrared Modulation/Demodulation 2 C Compatible Devices Supported ...
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... Description Atmel's AT91SAM7X512/256/128 is a member of a series of highly integrated Flash microcon- trollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components ...
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... AT91SAM7X512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADVREF AT91SAM7X512/256/128 Preliminary 4 AT91SAM7X512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK System Controller TST ...
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... Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ1 External Interrupt Inputs FIQ Fast Interrupt Input PA0 - PA30 Parallel IO Controller A PB0 - PB30 Parallel IO Controller B 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Active Type Level Power Power Power Power Power Power Power Ground Clocks, Oscillators and PLLs ...
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... SPIx_MOSI Master Out Slave In SPIx_SPCK SPI Serial Clock SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select TWD Two-wire Serial Data TWCK Two-wire Serial Clock AT91SAM7X512/256/128 Preliminary 6 Active Type USB Device Port Analog Analog USART I/O I/O Input Output Input ...
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... Collision Detected EMDC Management Data Clock EMDIO Management Data Input/Output EF100 Force 100 Mbits/sec. Section 6. ”I/O Lines Considerations” Note: 1. Refer to 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Type Analog-to-Digital Converter Analog Analog Input Analog Fast Flash Programming Interface Input Input I/O Output ...
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... Package The AT91SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS- compliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section. Figure 4-1. AT91SAM7X512/256/128 Preliminary 8 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip- 100-lead LQFP Package Outline (Top View) ...
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... GND 41 17 VDDIO 42 18 PA10/PGMM2 43 19 PA11/PGMM3 44 20 PA12/PGMD0 45 21 PA13/PGMD1 46 22 PA14/PGMD2 47 23 PA15/PGMD3 48 24 PA16/PGMD4 49 25 PA17/PGMD5 50 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PA18/PGMD6 51 PB9 52 PB8 53 PB14 54 PB13 55 PA23/PGMD11 PB6 56 PA24/PGMD12 GND 57 VDDIO 58 PB5 59 PA25/PGMD13 PB15 60 PA26/PGMD14 PB17 61 VDDCORE 62 PB7 ...
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... PA14/PGMD2 E3 B9 PA16/PGMD4 E4 B10 PA17/PGMD5 E5 C1 PB16 E6 C2 PB4 E7 C3 PB10 E8 C4 PB3 E9 C5 PB0 E10 AT91SAM7X512/256/128 Preliminary 10 shows the orientation of the 100-ball TFBGA package. A detailed mechanical 100-ball TFBGA Package Outline (Top View BALL A1 Signal Name Pin Signal Name PB17 F1 PB13 ...
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... Power Consumption The AT91SAM7X512/256/128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. ...
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... For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The AT91SAM7X512/256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. shows the power schematics to be used for USB bus-powered systems. ...
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... Test Pin AT91SAM7X512/256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND. To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to GND if the FFPI is not used, or pulled down with an external low-value resistor (such as 1 kΩ) To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low ...
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... The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. AT91SAM7X512/256/128 Preliminary 14 6120H–ATARM–17-Feb-09 ...
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... Facilitates debug by detection of bad pointers • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Controller 15 ...
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... One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements • Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest): AT91SAM7X512/256/128 Preliminary 16 wait states Receive ...
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... Full chip erase time – 10,000 write cycles, 10-year data retention capability – 8 lock bits, each protecting 8 sectors of 64 pages – Protection Mode to secure contents of the Flash • 32 Kbytes of Fast SRAM – Single-cycle access at full speed 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 17 ...
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... Figure 8-1. AT91SAM7X512/256/128 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF AT91SAM7X512/256/128 Preliminary 18 Internal Memory Mapping 0x0000 0000 ...
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... After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The AT91SAM7X512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA program. 8.4.3 Internal Flash • ...
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... Embedded Flash 8.5.1 Flash Overview • The Flash of the AT91SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the AT91SAM7X256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. ...
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... Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.4 Security Bit Feature The AT91SAM7X512/256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast 6120H–ATARM–17-Feb-09 ...
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... The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in- situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. • Communication via the DBGU supports a wide range of crystals from MHz via software auto-detection. AT91SAM7X512/256/128 Preliminary 22 6120H–ATARM–17-Feb-09 ...
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... The SAM-BA Boot is in ROM and is mapped at address 0x0 when the GPNVM Bit 2 is set to 0. When GPNVM bit 2 is set to 1, the device boots from the Flash. When GPNVM bit 2 is set to 0, the device boots from ROM (SAM-BA). 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 23 ...
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... Figure 9-1 on page 25 Figure 8-1 on page 18 erals. Note that the Memory Controller configuration user interface is also mapped within this address space. AT91SAM7X512/256/128 Preliminary 24 shows the System Controller Block Diagram. shows the mapping of the User Interface of the System Controller periph- 6120H–ATARM–17-Feb-09 ...
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... Figure 9-1. NRST XOUT PLLRC PA0-PA30 PB0-PB30 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary System Controller Block Diagram System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset ...
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... Brownout Detector and Power-on Reset The AT91SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. ...
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... Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Clock Generator Block Diagram Clock Generator Embedded Oscillator XIN ...
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... Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive external • 8-level Priority Controller – Drives the normal interrupt nIRQ of the processor – Handles priority of the interrupt sources AT91SAM7X512/256/128 Preliminary 28 Power Management Controller Block Diagram Master Clock Controller SLCK ...
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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x275C 0A40 (VERSION 0) for AT91SAM7X512 – Chip ID is 0x275B 0940 (VERSION 0) for AT91SAM7X256 – Chip ID is 0x275A 0740 (VERSION 0) for AT91SAM7X128 9 ...
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... Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). AT91SAM7X512/256/128 Preliminary 30 6120H–ATARM–17-Feb-09 ...
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... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 Peripheral Identifiers The AT91SAM7X512/256/128 embeds a wide range of peripherals. Peripheral Identifiers of the AT91SAM7X512/256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID 0 ...
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... Peripheral Multiplexing on PIO Lines The AT91SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func- tions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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... CANTX PA21 TF PA22 TK PA23 TD PA24 RD PA25 RK PA26 RF PA27 DRXD PA28 DTXD PA29 FIQ PA30 IRQ0 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Peripheral B Comments High-Drive High-Drive SPI1_NPCS1 High-Drive SPI1_NPCS2 High-Drive SPI1_NPCS3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 PCK1 IRQ1 TCLK2 SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 ...
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... PB21 PWM2 PB22 PWM3 PB23 TIOA0 PB24 TIOB0 PB25 TIOA1 PB26 TIOB1 PB27 TIOA2 PB28 TIOB2 PB29 PCK1 PB30 PCK2 AT91SAM7X512/256/128 Preliminary 34 Peripheral B Comments PCK0 SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 RI1 ...
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... Selectable mode fault detection – Maximum frequency Master Clock 10.8 Two-wire Interface • Master Mode only • Compatibility with I 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary peripherals Sensors between clock and data 2 C compatible devices (refer to the TWI section of the datasheet) ® ...
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... Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.11 Timer Counter • Three 16-bit Timer Counter Channels – Two output compare or one input capture per channel • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement AT91SAM7X512/256/128 Preliminary 36 6120H–ATARM–17-Feb-09 ...
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... Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 256 bytes ping-pong – Ping-pong Mode (two memory banks) for bulk endpoints 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Table 10-4 Timer Counter Clocks Assignment Clock MCK/2 MCK/8 ...
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... External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all • Four of eight analog inputs shared with digital signals AT91SAM7X512/256/128 Preliminary 38 enabled channels 6120H–ATARM–17-Feb-09 ...
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... Two Instruction Sets – ARM – Thumb • Three-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ® High-performance 32-bit Instruction Set ® High Code Density 16-bit Instruction Set ® ® and 16-bit Thumb ...
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... At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer. AT91SAM7X512/256/128 Preliminary 40 6120H–ATARM–17-Feb-09 ...
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... R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers that interrupt processing can begin with- out having to save these registers. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ARM7TDMI ARM Modes and Registers Layout Supervisor Mode Abort Mode ...
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... Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 11-2 AT91SAM7X512/256/128 Preliminary 42 supports five types of exception and a privileged processing mode for each type. gives the ARM instruction mnemonic list. 6120H–ATARM–17-Feb-09 ...
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... In Thumb mode, eight general-purpose registers R7, are available that are the same physical registers when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ARM Instruction Mnemonic List Operation Move ...
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... TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH AT91SAM7X512/256/128 Preliminary 44 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right ...
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... Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram PDC 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ICE/JTAG Boundary TAP TAP ICE ARM7TDMI DBGU ...
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... Application Examples 12.3.1 Debug Environment Figure 12-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example AT91SAM7X512/256/128 Preliminary 46 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 ...
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... NRST TST TCK TDI TDO TMS JTAGSEL DRXD DTXD 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary shows a test environment example. Test vectors are sent and interpreted by the tes- Test Adaptor JTAG Interface ICE/JTAG Chip n Connector AT91SAM7Xxx AT91SAM7Xxx-based Application Board In Test Debug and Test Pin List ...
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... A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7X512 Debug Unit Chip ID value is 0x275C 0A40 on 32-bit width. The AT91SAM7X256 Debug Unit Chip ID value is 0x275B 0940 on 32-bit width. The AT91SAM7X128 Debug Unit Chip ID value is 0x275A 0740 on 32-bit width. ...
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... The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-2. Number 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register Bit Pin Name 187 ...
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... Table 12-2. Number AT91SAM7X512/256/128 Preliminary 50 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 163 162 PA7/SCK1/SPI0_NPCS1 161 160 ERASE 159 158 PB27/TIOA2/PWM0/AD0 157 156 155 PB28/TIOB2/PWM1/AD1 154 153 152 PB29/PCK1/PWM2/AD2 151 150 149 PB30/PCK2/PWM3/AD3 148 147 146 PA8/RTS1/SPI0_NPCS2 145 144 ...
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... Table 12-2. Number 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 129 128 PA14/SPI0_NPCS2/IRQ1 127 126 125 PA15/SPI0_NPCS3/TCLK2 124 123 122 PA16/SPI0_MISO 121 120 119 PA17/SPI0_MOSI 118 117 116 PA18/SPI0_SPCK 115 114 113 PB9/EMDIO 112 ...
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... Table 12-2. Number AT91SAM7X512/256/128 Preliminary 52 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 96 95 PB15/ERXDV/ECRSDV PB17/ERXCK/SPI0_NPCS3 PB7/ERXER PB12/ETXER/TCLK0 PB0/ETXCK/EREFCK/PCK0 PB1/ETXEN PB2/ETX0 PB3/ETX1 PB10/ETX2/SPI1_NPCS1 PB11/ETX3/SPI1_NPCS2 PA19/CANRX 64 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT ...
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... Table 12-2. Number 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 63 62 PA20/CANTX PA21/TF/SPI1_NPCS0 PA22/TK/SPI1_SPCK PB16/ECOL/SPI1_NPCS3 PB4/ECRS PA23/TD/SPI1_MOSI PA24/RD/SPI1_MISO PA25/RK/SPI1_NPCS1 PA26/RF/SPI1_NPCS2 PB18/EF100/ADTRG PB19/PWM0/TCLK1 31 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT ...
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... Table 12-2. Number AT91SAM7X512/256/128 Preliminary 54 AT91SAM7X JTAG Boundary Scan Register (Continued) Bit Pin Name 30 29 PB20/PWM1/PCK0 PB21/PWM2/PCK2 PB22/PWM3/PCK2 PB23/TIOA0/DCD1 PB24/TIOB0/DSR1 PB25/TIOA1/DTR1 PB26/TIOB1/RI1 PA27DRXD/PCK3 PA28/DTXD PA29/FIQ/SPI1_NPCS3 1 Associated BSR Pin Type Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT OUTPUT ...
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... PART NUMBER[27:12]: Product Part Number AT91SAM7X512: 0x5B18 AT91SAM7X256: 0x5B17 AT91SAM7X128: 0x5B16 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. AT91SAM7X512: JTAG ID Code value is 05B1_803F AT91SAM7X256: JTAG ID Code value is 05B1_703F AT91SAM7X128: JTAG ID Code value is 05B1_303F 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ...
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... AT91SAM7X512/256/128 Preliminary 56 6120H–ATARM–17-Feb-09 ...
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... A brownout detection is also available to prevent the processor from falling into an unpredictable state. 13.1 Block Diagram Figure 13-1. Reset Controller Block Diagram Main Supply 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Reset Controller bod_rst_en Brownout Manager brown_out Startup POR Counter ...
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... As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset so, the bit URSTIEN in RSTC_MR must be written at 1. AT91SAM7X512/256/128 Preliminary 58 Figure 13-2 shows the block diagram of the NRST Manager. ...
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... The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 13-3. Brownout Manager 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs bod_rst_en RSTC_SR brown_out ...
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... When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately. Figure 13-4. Power-up Reset SLCK MCK Main Supply POR output proc_nreset periph_nreset NRST (nrst_out) AT91SAM7X512/256/128 Preliminary 60 Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator Startup Time Processor Startup = 3 cycles EXTERNAL RESET LENGTH = 2 cycles Any Freq. ...
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... NRST actually rises. Figure 13-5. User Reset State SLCK Any MCK Freq. NRST Resynch. 2 cycles proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH Processor Startup = 3 cycles 0x4 = User Reset ...
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... Brownout Reset. Figure 13-6. Brownout Reset State SLCK Any MCK Freq. brown_out or bod_reset proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) AT91SAM7X512/256/128 Preliminary 62 Resynch. Processor Startup 2 cycles = 3 cycles XXX 0x5 = Brownout Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 6120H–ATARM–17-Feb-09 ...
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... As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 63 ...
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... Figure 13-7. Software Reset AT91SAM7X512/256/128 Preliminary 64 SLCK Any MCK Freq. Write RSTC_CR Resynch. 1 cycle proc_nreset if PROCRST=1 RSTTYP Any periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 SRCMP in RSTC_SR Processor Startup = 3 cycles XXX 0x3 = Software Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 6120H–ATARM–17-Feb-09 ...
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... Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 13-8. Watchdog Reset Only if WDRPROC = 0 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary SLCK Any MCK Freq. wd_fault proc_nreset ...
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... A watchdog event has priority over the current state. – The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. AT91SAM7X512/256/128 Preliminary 66 proc_nreset signal. 6120H–ATARM–17-Feb-09 ...
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... Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. Figure 13-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 2 cycle resynchronization Figure read RSTC_SR 67 ...
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... Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register AT91SAM7X512/256/128 Preliminary 68 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset - 0x0000_0000 0x0000_0000 6120H–ATARM–17-Feb-09 ...
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... No effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary KEY – ...
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... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. AT91SAM7X512/256/128 Preliminary – ...
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... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary KEY ...
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... AT91SAM7X512/256/128 Preliminary 72 6120H–ATARM–17-Feb-09 ...
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... Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary set 0 RTT_SR RTTINC ...
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... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM7X512/256/128 Preliminary 74 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
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... Real-time Timer (RTT) User Interface Table 14-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Name RTT_MR RTT_AR RTT_VR RTT_SR Access Reset Value Read-write 0x0000_8000 Read-write 0xFFFF_FFFF Read-only 0x0000_0000 ...
Page 76
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM7X512/256/128 Preliminary – ...
Page 77
... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.4.3 Real-time Timer Value Register Register Name: RTT_VR Access Type: Read-only • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ALMV ALMV ALMV ALMV 29 ...
Page 78
... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM7X512/256/128 Preliminary – ...
Page 79
... Block Diagram Figure 15-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR set 0 PIT_SR PITS reset 0 ...
Page 80
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. AT91SAM7X512/256/128 Preliminary 80 Figure 15-2 illustrates 6120H– ...
Page 81
... Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler ...
Page 82
... Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM7X512/256/128 Preliminary 82 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset ...
Page 83
... PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – – ...
Page 84
... Register Name: PIT_PIIR Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91SAM7X512/256/128 Preliminary PICNT CPIV CPIV ...
Page 85
... Block Diagram Figure 16-1. Watchdog Timer Block Diagram write WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD ...
Page 86
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM7X512/256/128 Preliminary 86 6120H–ATARM–17-Feb-09 ...
Page 87
... Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
Page 88
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7X512/256/128 Preliminary 88 Name WDT_CR WDT_MR WDT_SR KEY – – ...
Page 89
... WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary WDDBGHLT 21 20 ...
Page 90
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM7X512/256/128 Preliminary – ...
Page 91
... Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset wake up the Voltage Regulator in Normal Mode. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 91 ...
Page 92
... VREG_MR Access Type: Read-write 31 30 – – – – – – – – • PSTDBY: Periodic Interval Value 0 = Voltage regulator in normal mode Voltage regulator in standby mode (low-power mode). AT91SAM7X512/256/128 Preliminary 92 Name VREG_MR – – – – – – – – – ...
Page 93
... Embedded Flash Controller. 18.2 Block Diagram Figure 18-1. Memory Controller Block Diagram ARM7TDMI Processor Abort EMAC DMA Peripheral DMA Controller 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Memory Controller ASB Abort Status Address Misalignment Decoder Bus Detector Arbiter User Interface ...
Page 94
... One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed Figure 18-2 Figure 18-2. Memory Areas AT91SAM7X512/256/128 Preliminary 94 shows the assignment of the 256-Mbyte memory areas. 0x0000 0000 256M Bytes ...
Page 95
... The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 0x0000 0000 Internal Memory Area 0 0x000F FFFF ...
Page 96
... Note that the accesses of the ARM processor when it is fetching instructions are not checked. AT91SAM7X512/256/128 Preliminary 96 6120H–ATARM–17-Feb-09 ...
Page 97
... As the requested address is saved in the Abort Status Register and the address of the instruc- tion generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 97 ...
Page 98
... MC Abort Status Register 0x08 MC Abort Address Status Register 0x10-0x5C Reserved 0x60 EFC0 Configuration Registers (1) 0x70 EFC1 Configuration Registers Note: 1. EFC1 pertains to AT91SAM7X512 only. AT91SAM7X512/256/128 Preliminary 98 Name Access MC_RCR Write-only MC_ASR Read-only MC_AASR Read-only See the Embedded Flash Controller Section Reset State ...
Page 99
... RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – – – – ...
Page 100
... ABTSZ • ABTTYP: Abort Type Status ABTTYP • MST_EMAC: EMAC Abort Source 0: The last aborted access was not due to the EMAC. 1: The last aborted access was due to the EMAC. AT91SAM7X512/256/128 Preliminary 100 – – – – – – – – – ...
Page 101
... At least one abort due to the PDC occurred since the last read of MC_ASR. • SVMST_ARM: Saved ARM Abort Source 0: No abort due to the ARM occurred since the last read of MC_ASR notified in the bit MST_ARM least one abort due to the ARM occurred since the last read of MC_ASR. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 101 ...
Page 102
... MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 • ABTADD: Abort Address This field contains the address of the last aborted access. AT91SAM7X512/256/128 Preliminary 102 ABTADD ABTADD ABTADD ABTADD 6120H–ATARM–17-Feb-09 ...
Page 103
... Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM bits. The Security and GPNVM bits embedded only on EFC0 apply to the two blocks in the AT91SAM7X512 ...
Page 104
... The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. AT91SAM7X512/256/128 Preliminary 104 Flash Memory ...
Page 105
... Flash Access Buffer (32 bits) Data To ARM Note: When FWS is equal case of sequential reads, all the accesses are performed in a single-cycle access (except for the first one). 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary @Byte 8 @Byte 6 @Byte 4 Bytes 4-7 Bytes 8-11 Bytes 4-7 Bytes 0-3 ...
Page 106
... Table 19-2. Command Write page Set Lock Bit Write Page and Lock Clear Lock Bit Erase all Set General-purpose NVM Bit Clear General-purpose NVM Bit Set Security Bit AT91SAM7X512/256/128 Preliminary 106 3 Wait State Cycles 3 Wait State Cycles @ Bytes 4-7 Bytes 0-3 ...
Page 107
... When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 107 ...
Page 108
... NEBP bit in the MC_FMR register before writing the command in the MC_FCR register. By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased before (see AT91SAM7X512/256/128 Preliminary 108 Read Status: MC_FSR No ...
Page 109
... Lock Error: The page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region. 19.2.4.2 Erase All Command The entire memory can be erased if the Erase All Command (EA) in the Flash Command Regis- ter MC_FCR is written. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 32 bits wide ... ...
Page 110
... The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in MC_FSR reads 1. Note: AT91SAM7X512/256/128 Preliminary 110 Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed. 6120H–ATARM–17-Feb-09 ...
Page 111
... The goal of the security bit is to prevent external access to the internal bus system. (Does not apply to EFC1 on the AT91SAM7X512.) JTAG, Fast Flash Programming and Flash Serial Test Interface features are disabled. Once set, this bit can be reset only by an external hardware ERASE request to the chip ...
Page 112
... When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the security bit is active, the SECURITY bit in the MC_FSR is set. AT91SAM7X512/256/128 Preliminary 112 6120H–ATARM–17-Feb-09 ...
Page 113
... Embedded Flash Controller (EFC ) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register Mapping tables and Reg- ister descriptions that follow. ...
Page 114
... Programming Error generates an interrupt. • NEBP: No Erase Before Programming 0: A page erase is performed before programming erase is performed before programming. • FWS: Flash Wait State This field defines the number of wait states for read and write operations: FWS AT91SAM7X512/256/128 Preliminary 114 – – – ...
Page 115
... When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds. Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN) must be correctly programmed. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 115 ...
Page 116
... FCMD: Flash Command This field defines the Flash commands: FCMD 0000 0001 0010 0011 0100 1000 1011 1101 1111 Others AT91SAM7X512/256/128 Preliminary 116 KEY – – – PAGEN – – Operations No command. Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR. ...
Page 117
... This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is writ- ten with a different value, the write is not performed and no action is started. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PAGEN Description PAGEN defines the page number to be written. ...
Page 118
... SECURITY: Security Bit Status (Does not apply to EFC1 on the AT91SAM7X512.) 0: The security bit is inactive. 1: The security bit is active. • GPNVMx: General-purpose NVM Bit Status (Does not apply to EFC1 on the AT91SAM7X512.) 0: The corresponding general-purpose NVM bit is inactive. 1: The corresponding general-purpose NVM bit is active. ...
Page 119
... In Fast Flash Programming Mode, the device specific test mode. Only a certain set of pins is significant, the rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left unconnected. Figure 20-1. Parallel Programming Interface 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary TST VDDIO PGMEN0 VDDIO ...
Page 120
... Depending on the MODE settings, DATA is latched in different internal registers. Table 20-2. MODE[3:0] 0000 0001 0010 0101 Default When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. AT91SAM7X512/256/128 Preliminary 120 Type Power Power Power Power Power Ground Clocks ...
Page 121
... GGPB SSE GSE WRAM SEFC GVE 1. Applies to AT91SAM7X512 external clock is available. POR_RESET POR_RESET After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal external clock ( > 32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake ...
Page 122
... Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal 6 Waits for RDY high 20.2.4.2 Read Handshaking For details on the read handshaking sequence, refer to Figure 20-3. AT91SAM7X512/256/128 Preliminary 122 NCMD 2 3 RDY NOE NVALID DATA[15:0] 1 MODE[3:0] Device Action Waits for NCMD low ...
Page 123
... AT91SAM7X512/256/128 Preliminary Device Action Waits for NCMD low Latch MODE and DATA Clears RDY signal Waits for NOE Low Sets DATA bus in output mode and outputs the flash contents. Clears NVALID signal Waits for NOE high ...
Page 124
... This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 20-9. Step 1 2 AT91SAM7X512/256/128 Preliminary 124 Write Command Handshake Sequence MODE[3:0] Write handshaking CMDE ...
Page 125
... General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The n GP NVM bit is active when bit n of the bit mask is set.. Table 20-13. Get GP NVM Bit Command Step 1 2 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Handshake Sequence Write handshaking Write handshaking Handshake Sequence Write handshaking Read handshaking ...
Page 126
... Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The AT91SAM7X512 security bit is controlled by the EFC0. To use the Set Security Bit com- mand, the EFC0 must be selected using the Select EFC command Table 20-14 ...
Page 127
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-17. Get Version Command Step 1 2 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Handshake Sequence MODE[3:0] ... ... Write handshaking ADDR0 Write handshaking ADDR1 Write handshaking DATA ...
Page 128
... I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground Main Clock Input. This input can be tied to GND. In this XIN case, the device is clocked by the internal RC oscillator. AT91SAM7X512/256/128 Preliminary 128 VDDIO TST VDDIO PGMEN0 VDDIO PGMEN1 TDI TDO TMS TCK ...
Page 129
... Note: Table 20-19. Reset TAP Controller and Go to Select-DR-Scan 20.3.3 Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Type Test Input Input Input JTAG ...
Page 130
... Debug Comms Registers. 20.3.4.1 Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at AT91SAM7X512/256/128 Preliminary 130 r/w 4 Address ...
Page 131
... Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands. 20.3.4.3 Flash Full Erase Command This command is used to erase the Flash memory planes. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary DR Data (Number of Words to Read) << READ Address Memory [address] Memory [address+4] ...
Page 132
... GP NVM bits can be read using Get GPNVM Bit command (GGPB). When a bit set in the Bit Mask is returned, then the corresponding GPNVM bit is set. Table 20-26. Get General-purpose NVM Bit Command Read/Write Write Read AT91SAM7X512/256/128 Preliminary 132 DR Data EA DR Data SLB or CLB ...
Page 133
... Fast Flash programming is disabled. No other command can be run. Only an event on the Erase pin can erase the security bit once the contents of the Flash have been erased. The AT91SAM7X512 security bit is controlled by the EFC0. To use the Set Security Bit com- mand, the EFC0 must be selected using the Select EFC command. ...
Page 134
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-30. Get Version Command Read/Write Write Read AT91SAM7X512/256/128 Preliminary 134 DR Data GVE Version 6120H–ATARM–17-Feb-09 ...
Page 135
... PLL setup: PLL is initialized to generate a 48 MHz clock necessary to use the USB Device 9. Disable of the Watchdog and enable of the user reset 10. Initialization of the USB Device Port 11. Jump to SAM-BA Boot sequence (see 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary ® Boot is then executed. It waits for transactions either on the USB device the Device USB Enumeration Setup ...
Page 136
... The SAM-BA boot principle is to: – Check if USB Device enumeration has occurred – Check if the AutoBaudrate sequence has succeeded (see Figure 21-2. AutoBaudrate Flow Diagram – Once the communication interface is identified, the application runs in an infinite AT91SAM7X512/256/128 Preliminary 136 Device Setup Character '0x80' ...
Page 137
... The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Commands Available through the SAM-BA Boot Action Argument(s) ...
Page 138
... The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. AT91SAM7X512/256/128 Preliminary 138 to 01) shows a transmission using this protocol. ...
Page 139
... BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Handled Standard Requests Definition Returns the current device configuration value. ...
Page 140
... Hardware and Software Constraints • SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 122880 bytes forAT91SAM7x512, 57344 bytes for AT91SAM7X256 and 24576 bytes for AT91SAM7X128. • USB requirements: – ...
Page 141
... The peripheral triggers PDC transfers using transmit and receive signals. When the pro- grammed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. 22.2 Block Diagram Figure 22-1. Block Diagram 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Peripheral DMA Controller Peripheral THR PDC Channel 0 PDC Channel 1 RHR Status & ...
Page 142
... If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag. If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. AT91SAM7X512/256/128 Preliminary 142 6120H–ATARM–17-Feb-09 ...
Page 143
... If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 143 ...
Page 144
... PDC Transfer Status Register Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.). AT91SAM7X512/256/128 Preliminary 144 Name (1) PERIPH ...
Page 145
... RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: Read-write • RXCTR: Receive Counter Value Number of receive transfers to be performed. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary RXPTR RXPTR RXPTR RXPTR 29 28 ...
Page 146
... Address of the transmit buffer. 22.4.4 PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read-write • TXCTR: Transmit Counter Value TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral DMA transfer is stopped. AT91SAM7X512/256/128 Preliminary 146 TXPTR TXPTR TXPTR TXPTR ...
Page 147
... RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. 22.4.6 PDC Receive Next Counter Register Register Name: PERIPH_RNCR Access Type: Read-write • RXNCR: Receive Next Counter Value RXNCR is the size of the next buffer to receive. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary RXNPTR RXNPTR RXNPTR RXNPTR 29 ...
Page 148
... TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 22.4.8 PDC Transmit Next Counter Register Register Name: PERIPH_TNCR Access Type: Read-write • TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit. AT91SAM7X512/256/128 Preliminary 148 TXNPTR TXNPTR TXNPTR ...
Page 149
... RXTDIS: Receiver Transfer Disable effect Disables the receiver PDC transfer requests. • TXTEN: Transmitter Transfer Enable effect Enables the transmitter PDC transfer requests. • TXTDIS: Transmitter Transfer Disable effect Disables the transmitter PDC transfer requests 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – – – ...
Page 150
... RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled Receiver PDC transfer requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled Transmitter PDC transfer requests are enabled. AT91SAM7X512/256/128 Preliminary 150 – – – ...
Page 151
... The fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt. 23.2 Block Diagram Figure 23-1. Block Diagram 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary FIQ AIC IRQ0-IRQn Up to Thirty-two Sources Embedded ...
Page 152
... AIC Detailed Block Diagram Figure 23-3. AIC Detailed Block Diagram 23.5 I/O Line Description Table 23-1. I/O Line Description Pin Name FIQ IRQ0 - IRQn AT91SAM7X512/256/128 Preliminary 152 Standalone OS Drivers Applications General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals Advanced Interrupt Controller ...
Page 153
... The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 153 ...
Page 154
... The AIC_ISR register reads the number of the current interrupt (see 158) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. AT91SAM7X512/256/128 Preliminary 154 (See “Priority Controller” on page 158.) The automatic clear reduces See “ ...
Page 155
... Internal Interrupt Source Input Stage Figure 23-4. 23.7.1.6 External Interrupt Source Input Stage Figure 23-5. External Interrupt Source Input Stage Source i AIC_ISCR AIC_ICCR 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Source i Edge Edge Detector Set ...
Page 156
... The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 23.7.2.1 External Interrupt Edge Triggered Source Figure 23-6. AT91SAM7X512/256/128 Preliminary 156 External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ ...
Page 157
... External Interrupt Level Sensitive Source Figure 23-7. 23.7.2.3 Internal Interrupt Edge Triggered Source Figure 23-8. 23.7.2.4 Internal Interrupt Level Sensitive Source Figure 23-9. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ ...
Page 158
... This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus acces- sible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR AT91SAM7X512/256/128 Preliminary 158 PC,[PC,# -&F20] 6120H–ATARM–17-Feb-09 ...
Page 159
... For example, the instruction SUB PC, LR, #4 may be used. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary priority. The current level is the priority level of the current interrupt. must be read in order to de-assert nIRQ. 159 ...
Page 160
... PC. This has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: AT91SAM7X512/256/128 Preliminary 160 If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur- ing this phase. ...
Page 161
... ARM core adjusts R14_fiq, decre- menting it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PC,[PC,# -&F20] 161 ...
Page 162
... Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). AT91SAM7X512/256/128 Preliminary 162 The “F” bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted ...
Page 163
... Fast Interrupt sources. Figure 23-10. Fast Forcing Source 0 _ FIQ Input Stage Automatic Clear Source n Input Stage Automatic Clear 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary AIC_IPR AIC_IMR Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR AIC_IPR AIC_IMR Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n ...
Page 164
... AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: • An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. AT91SAM7X512/256/128 Preliminary 164 6120H–ATARM–17-Feb-09 ...
Page 165
... Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary 165 ...
Page 166
... The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. AT91SAM7X512/256/128 Preliminary 166 Name AIC_SMR0 ...
Page 167
... The priority level is not used for the FIQ in the related SMR register AIC_SMRx. • SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. SRCTYPE 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – – – – – ...
Page 168
... The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. AT91SAM7X512/256/128 Preliminary 168 29 28 ...
Page 169
... AIC_ISR Access Type: Read-only Reset Value – – – – – – – – • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary FIQV FIQV FIQV FIQV – – – 21 ...
Page 170
... Access Type: Read-only Reset Value PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. AT91SAM7X512/256/128 Preliminary 170 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 ...
Page 171
... AIC_IECR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID3: Interrupt Enable effect Enables corresponding interrupt. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – – – – – – – – – ...
Page 172
... Register Name: AIC_ICCR Access Type: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Clear effect Clears corresponding interrupt. AT91SAM7X512/256/128 Preliminary 172 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 ...
Page 173
... The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PID29 PID28 ...
Page 174
... PROT: Protection Mode 0 = The Protection Mode is disabled The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC The nIRQ and nFIQ lines are tied to their inactive state. AT91SAM7X512/256/128 Preliminary 174 SIVR 21 ...
Page 175
... PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Disable effect Disables the Fast Forcing feature on the corresponding interrupt. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 ...
Page 176
... PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt The Fast Forcing feature is enabled on the corresponding interrupt. AT91SAM7X512/256/128 Preliminary 176 PID29 PID28 PID27 PID21 PID20 PID19 13 12 ...
Page 177
... The typical crystal connection is illustrated in trical characteristics of the Main Oscillator, see the section “DC Characteristics” of the product datasheet. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary Section 25.9. However, the Clock Generator registers are named CKGR_. shows the Main Oscillator block diagram. ...
Page 178
... Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of AT91SAM7X512/256/128 Preliminary 178 AT91SAM7X Microcontroller ...
Page 179
... Values and connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary shows the block diagram of the divider and PLL block. DIV Divider ...
Page 180
... The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. AT91SAM7X512/256/128 Preliminary 180 6120H–ATARM–17-Feb-09 ...
Page 181
... This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Figure 25-1. Master Clock Controller MAINCK PLLCK 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PMC_MCKR PMC_MCKR CSS SLCK Master Clock ...
Page 182
... In order to stop a peripheral recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data cor- ruption or erroneous behavior of the system. AT91SAM7X512/256/128 Preliminary 182 USBDIV USB ...
Page 183
... This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary write_register(CKGR_MOR,0x00000701) 183 ...
Page 184
... MCKRDY has been enabled in the PMC_IER register. The PMC_MCKR register must not be programmed in a single write operation. The pre- ferred programming sequence for the PMC_MCKR register is as follows: AT91SAM7X512/256/128 Preliminary 184 write_register(CKGR_PLLR,0x00040805) 6120H–ATARM–17-Feb-09 ...
Page 185
... The PRES field is used to control the Programmable clock prescaler possible to choose between different values ( 16, 32, 64). Programmable clock output is prescaler 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set ...
Page 186
... Depending on the system used, 15 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. AT91SAM7X512/256/128 Preliminary 186 Each enabled peripheral clock corresponds to Master Clock. 6120H–ATARM–17-Feb-09 ...
Page 187
... Clock Switching Waveforms Figure 25-3. Switch Master Clock from Slow Clock to PLL Clock Write PMC_MCKR 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary gives the worst case timings required for the Master Clock to switch from one Clock Switching Timings (Worst Case) From Main Clock – ...
Page 188
... Figure 25-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR Figure 25-5. Change PLL Programming Write CKGR_PLLR AT91SAM7X512/256/128 Preliminary 188 Slow Clock Main Clock MCKRDY Master Clock Main Clock PLL Clock LOCK MCKRDY Master Clock Main Clock 6120H–ATARM–17-Feb-09 ...
Page 189
... Figure 25-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PLL Clock PCKRDY PCKx Output PLL Clock is selected PCKx is enabled PCKx is disabled 189 ...
Page 190
... Programmable Clock 0 Register 0x0044 Programmable Clock 1 Register ... ... 0x0060 Interrupt Enable Register 0x0064 Interrupt Disable Register 0x0068 Status Register 0x006C Interrupt Mask Register 0x0070 - 0x007C Reserved AT91SAM7X512/256/128 Preliminary 190 Name Access PMC_SCER Write-only PMC_SCDR Write-only PMC _SCSR Read-only – – PMC _PCER Write-only PMC_PCDR ...
Page 191
... UDP – • UDP: USB Device Port Clock Enable effect Enables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Enable effect Enables the corresponding Programmable Clock output. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – – – ...
Page 192
... Disables the Processor clock. This is used to enter the processor in Idle Mode. • UDP: USB Device Port Clock Disable effect Disables the 48 MHz clock of the USB Device Port. • PCKx: Programmable Clock x Output Disable effect Disables the corresponding Programmable Clock output. AT91SAM7X512/256/128 Preliminary 192 – – ...
Page 193
... The 48 MHz clock (UDPCK) of the USB Device Port is disabled The 48 MHz clock (UDPCK) of the USB Device Port is enabled. • PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled The corresponding Programmable Clock output is enabled. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – ...
Page 194
... PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Disable effect Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. AT91SAM7X512/256/128 Preliminary 194 PID29 PID28 PID27 PID21 PID20 PID19 ...
Page 195
... PID7 PID6 • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled The corresponding peripheral clock is enabled. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary PID29 PID28 PID27 PID21 ...
Page 196
... When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set. Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag. • OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time. AT91SAM7X512/256/128 Preliminary 196 – ...
Page 197
... Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled The Main Oscillator has been enabled previously and MAINF value is available. 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – ...
Page 198
... To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char- acteristics section of the product datasheet. • MUL: PLL Multiplier 0 = The PLL is deactivated 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1. • USBDIV: Divider for USB Clock USBDIV AT91SAM7X512/256/128 Preliminary 198 USBDIV – MUL PLLCOUNT ...
Page 199
... PMC_MCKR Access Type: Read-write 31 30 – – – – – – – – • CSS: Master Clock Selection • PRES: Processor Clock Prescaler 6120H–ATARM–17-Feb-09 AT91SAM7X512/256/128 Preliminary – – – – – – – – – – PRES CSS PRES ...
Page 200
... CSS: Master Clock Selection CSS • PRES: Programmable Clock Prescaler AT91SAM7X512/256/128 Preliminary 200 – – – – – – – – – – PRES Clock Source Selection 0 Slow Clock is selected 1 Main Clock is selected ...