AT91SAM9XE256-CU Atmel, AT91SAM9XE256-CU Datasheet

MCU ARM9 256K FLASH 217-BGA

AT91SAM9XE256-CU

Manufacturer Part Number
AT91SAM9XE256-CU
Description
MCU ARM9 256K FLASH 217-BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM9XE256-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, EBI, I2S, SPI, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
96
Number Of Timers
6
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
For Use With
AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9XE256-CU
Manufacturer:
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AT91SAM9XE256-CU
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Features
Incorporates the ARM926EJ-S
Additional Embedded Memories
Enhanced Embedded Flash Controller (EEFC)
External Bus Interface (EBI)
USB 2.0 Full Speed (12 Mbits per second) Device Port
USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device
and Double Port in 217-ball LFBGA Device
Ethernet MAC 10/100 Base-T
Image Sensor Interface
Bus Matrix
Fully-featured System Controller, including
– DSP instruction Extensions, ARM Jazelle
– 8 Kbytes Data Cache, 16 Kbytes Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE
– One 32-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– One 32-Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16-Kbyte (for
– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128,
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash
– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
– Media Independent Interface or Reduced Media Independent Interface
– 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
– Six 32-bit-layer Matrix
– Remap Command
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed
AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024
Pages of 512 Bytes Respectively.
Interface
• 128-bit Wide Access
• Fast Read Time: 45 ns
• Page Programming Time: 4 ms, Including Page Auto-erase,
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash
Full Erase Time: 10 ms
Security Bit
, Debug Communication Channel Support
ARM
®
Thumb
®
®
Technology for Java
Processor
®
Acceleration
AT91 ARM
Thumb
Microcontrollers
AT91SAM9XE128
AT91SAM9XE256
AT91SAM9XE512
Preliminary
6254C–ATARM–22-Jan-10

Related parts for AT91SAM9XE256-CU

AT91SAM9XE256-CU Summary of contents

Page 1

... Additional Embedded Memories – One 32-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32-Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16-Kbyte (for AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed – 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512 Respectively ...

Page 2

Reset Controller (RSTC) – Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control • Clock Generator (CKGR) – Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing ...

Page 3

IEEE • Required Power Supplies: – 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or ...

Page 4

AT91SAM9XE128/256/512 Block Diagram The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in on PIO Controller A” on page PIO Controller C” ...

Page 5

Figure 2-1. AT91SAM9XE128/256/512 Block Diagram 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Filter 5 ...

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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP0 Peripherals I/O Lines Power Supply VDDIOP1 Peripherals I/O Lines Power Supply VDDBU Backup I/O Lines Power Supply VDDANA Analog Power ...

Page 7

Table 3-1. Signal Description List (Continued) Signal Name Function Flash and NVM Configuration Bits ERASE Erase Command NRST Microcontroller Reset TST Test Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ0 - IRQ2 External Interrupt Inputs FIQ Fast ...

Page 8

Table 3-1. Signal Description List (Continued) Signal Name Function CFCE1 - CFCE2 CompactFlash Chip Enable CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 - CFCS1 CompactFlash ...

Page 9

Table 3-1. Signal Description List (Continued) Signal Name Function TD SSC Transmit Data RD SSC Receive Data TK SSC Transmit Clock RK SSC Receive Clock TF SSC Transmit Frame Sync RF SSC Receive Frame Sync TCLKx TC Channel x External ...

Page 10

Table 3-1. Signal Description List (Continued) Signal Name Function ETXCK Transmit Clock or Reference Clock ERXCK Receive Clock ETXEN Transmit Enable ETX0-ETX3 Transmit Data ETXER Transmit Coding Error ERXDV Receive Data Valid ERX0-ERX3 Receive Data ERXER Receive Error ECRS Carrier ...

Page 11

Package and Pinout The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch 217-ball LFBGA Green package (0.8 mm ball pitch). 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given ...

Page 12

PQFP Package Pinout Table 4-1. Pinout for 208-pin PQFP Package Pin Signal Name Pin 1 PA24 53 2 PA25 54 3 PA26 55 4 PA27 56 5 VDDIOP0 57 6 GND 58 7 PA28 59 8 PA29 60 ...

Page 13

LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character- istics” of the product datasheet. Figure 4-2. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary shows the orientation of the 217-ball LFBGA package. 217-ball LFBGA Package ...

Page 14

LFBGA Package Pinout Table 4-2. Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 CFIOW/NBS3/NWR3 D5 A2 NBS0/ NWR2/NBS2/ A11 D10 A7 A13 D11 A8 BA0/A16 D12 ...

Page 15

Power Considerations 5.1 Power Supplies The AT91SAM9XE128/256/512 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal. • VDDIOM ...

Page 16

MΩ. The resisitor value is calculated according to the regulator enable implementation and the SHDN level. The WKUP pin is an input-only. It can accept voltages only between 0V and VDDBU. 7. Processor and Architecture 7.1 ARM926EJ-S Processor • ...

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Bus Matrix • 6-layer Matrix, handling requests from 6 masters • Programmable Arbitration strategy – Fixed-priority Arbitration – Round-Robin Arbitration, either with no default master, last accessed default master • Burst Management – Breaking with Slot Cycle Limit Support ...

Page 18

Table 7-2. Slave 3 Slave 4 Slave 5 7.2.3 Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the internal ...

Page 19

USART2 Transmit Channel – USART1 Transmit Channel – USART0 Transmit Channel – SPI1 Transmit Channel – SPI0 Transmit Channel – SSC Transmit Channel – TWI0 Receive Channel – TWI1 Receive Channel – DBGU Receive Channel – USART4 Receive Channel ...

Page 20

Memories Figure 8-1. AT91SAM9XE128/256/512 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 ...

Page 21

... Single Cycle Access at full matrix speed • 16 Kbytes Fast SRAM – Single Cycle Access at full matrix speed • 128 Kbytes Embedded Flash 8.1.2 AT91SAM9XE256 • 32 Kbytes ROM – Single Cycle Access at full matrix speed • 32 Kbytes Fast SRAM – Single Cycle Access at full matrix speed • ...

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TST pin and PA0 to PA3 pins. shows the contents of the ROM and the program available at address zero. Figure 8-2. ROM Boot Memory Map 0x0000 0000 SAM-BA Program FFPI ...

Page 23

Communication through the DBGU supports a wide range of crystals from MHz via software auto-detection. • Communication through the USB Device Port is depends on crystal selected: – limited to an 18,432 Hz crystal if the ...

Page 24

Figure 8-3. Flash First Memory Plane Mapping 0x0020 0000 Locked Regions Area 128, 256 or 512 Kbytes 256, 512 or 1024 Pages 0x0021 FFFF or 0x0023 FFFF or 0x0027 FFFF 8.1.5.3 GPNVM Bits The AT91SAM9XE128/256/512 features four GPNVM bits that ...

Page 25

Non-volatile Brownout Detector Control Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. • GPNVMBit[1] is used as a brownout detector enable ...

Page 26

GPNVMBit[ Boot on Internal Flash • Boot on slow clock (On-chip RC oscillator or 32,768 Hz low-power oscillator) The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz, ...

Page 27

SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit ...

Page 28

System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...

Page 29

System Controller Block Diagram Figure 9-1. AT91SAM9XE128/256/512 System Controller Block Diagram periph_irq[2..24] efc2_irq pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset BOD VDDCORE VDDCORE POR NRST VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSCSEL SLOW XIN32 CLOCK ...

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Reset Controller • Based on two Power-on reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software • Controls the internal resets ...

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Clock Generator • Embeds a low power 32,768 Hz slow clock oscillator and a low-power RC oscillator selectable with OSCSEL signal – Provides the permanent slow clock SLCK to the system • Embeds the main oscillator – Oscillator bypass ...

Page 32

... Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – ...

Page 33

Chip Identification • Chip ID: – 0x329AA3A0 for the SAM9XE512 – 0x329A93A0 for the SAM9XE256 – 0x329973A0 for the SAM9XE128 • JTAG ID: 05B1_C03F • ARM926 TAP ID: 0x0792603F 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 33 ...

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Peripherals 10.1 User Interface The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map ...

Page 35

Peripheral Interrupts and Clock Control 10.2.1.1 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-time ...

Page 36

PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A Peripheral B PA0 SPI0_MISO MCDB0 PA1 SPI0_MOSI MCCDB PA2 SPI0_SPCK PA3 SPI0_NPCS0 MCDB3 PA4 RTS2 MCDB2 PA5 CTS2 MCDB1 PA6 MCDA0 ...

Page 37

PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 SPI1_MISO PB1 SPI1_MOSI PB2 SPI1_SPCK PB3 SPI1_NPCS0 PB4 TXD0 PB5 RXD0 PB6 TXD1 PB7 RXD1 PB8 TXD2 PB9 RXD2 PB10 ...

Page 38

PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A Peripheral B PC0 SCK3 PC1 PCK0 (1) PC2 PCK1 (1) PC3 SPI1_NPCS3 PC4 A23 SPI1_NPCS2 PC5 A24 SPI1_NPCS1 PC6 TIOB2 CFCE1 ...

Page 39

Embedded Peripherals 10.4.1 Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, ...

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IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.4.4 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs ...

Page 41

USB Host Port • Compliance with Open HCI Rev 1.0 Specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices • Root hub integrated with two downstream USB ...

Page 42

Preview scaler to generate smaller size image 10.4.11 Analog-to-digital Converter • 4-channel ADC • 10-bit 312K samples/sec. Successive Approximation Register ADC • -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity • Individual enable and disable of each ...

Page 43

ARM926EJ-S Processor 11.1 Overview The ARM926EJ-S processor is a member of the ARM9 sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, low die size and low ...

Page 44

Block Diagram Figure 11-1. ARM926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor Write Data DTCM Interface Data TCM Data Cache AT91SAM9XE128/256/512 Preliminary 44 External Coprocessors External Coprocessor Interface ARM9EJ-S Processor Core Instruction Read Data Data Instruction Address Address ...

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ARM9EJ-S Processor 11.3.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable ...

Page 46

Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. ...

Page 47

ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers. • 31 general-purpose 32-bit registers • 6 32-bit status registers Table 11-2 Table 11-2. User and System Mode ...

Page 48

BL or BLX instructions are executed within interrupt or exception routines. There is another reg- ister called Saved Program Status Register (SPSR) that becomes ...

Page 49

The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an ...

Page 50

Preserves the address of the next instruction in the appropriate Link Register that cor- responds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address ...

Page 51

Table gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary ...

Page 52

New ARM Instruction Set . Table 11-3. Mnemonic BXJ BLX SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB Notes: 11.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The ...

Page 53

Table 11-4. Mnemonic AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC 11.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: ...

Page 54

Table 11-5. Register Notes: AT91SAM9XE128/256/512 Preliminary 54 CP15 Registers Name 7 Cache Operations 8 TLB operations (2) 9 cache lockdown 9 TCM region 10 TLB lockdown 11 Reserved 12 Reserved (1) 13 FCSE PID (1) 13 Context ID 14 Reserved ...

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CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) ...

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Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operating systems like Symbian ® Linux . These virtual memory features are memory access permission controls and ...

Page 57

Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does ...

Page 58

Caches and Write Buffer The ARM926EJ-S contains a 16-Kbyte Instruction Cache (ICache), a 8-Kbyte Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and ...

Page 59

DCache can be enabled or disabled by writing either 1 ...

Page 60

... The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. ...

Page 61

AT91SAM9XE Debug and Test 12.1 Overview The AT91SAM9XE features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The ...

Page 62

Block Diagram Figure 12-1. Debug and Test Block Diagram TAP: Test Access Port AT91SAM9XE128/256/512 Preliminary 62 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD DRXD ...

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Application Examples 12.3.1 Debug Environment Figure 12-2 on page 63 face is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for ...

Page 64

Test Environment Figure 12-3 on page 64 preted by the tester. In this example, the “board in test” is designed using a number of JTAG- compliant devices. These devices can be connected to form a single scan chain. Figure ...

Page 65

JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the ...

Page 66

IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ...

Page 67

Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 285 A19 284 283 A2 282 281 A20 280 279 A21 278 277 A22 276 275 A3 274 273 A4 272 271 A5 270 269 A6 268 267 A7 266 265 ...

Page 68

Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 ...

Page 69

Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 207 PA0 206 205 PA1 204 203 PA10 202 201 PA11 200 199 PA12 198 197 PA13 196 195 PA14 194 193 PA15 192 191 PA16 190 189 PA17 188 187 ...

Page 70

Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 ...

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Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 127 PB16 126 125 PB17 124 123 PB18 122 121 PB19 120 119 PB2 118 117 PB20 116 115 PB21 114 113 PB22 112 111 PB23 110 109 PB24 108 107 ...

Page 72

Table 12-2.AT91SAM9XE JTAG Boundary Scan Register AT91SAM9XE128/256/512 Preliminary 72 87 PB6 86 85 PB7 84 83 PB8 82 81 PB9 80 79 PC0 78 77 PC1 76 75 PC10 74 73 PC11 PC13 68 67 PC14 ...

Page 73

Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 47 PC23 46 45 PC24 44 43 PC25 42 41 PC26 40 39 PC27 38 37 PC28 36 35 PC29 PC30 30 29 PC31 28 27 PC4 ...

Page 74

Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 12.6.5 JID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number ...

Page 75

AT91SAM9XE Boot Program 13.1 Overview The Boot Program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA Boot ...

Page 76

Device Initialization Initialization follows the steps described below: 1. FIQ Initialization 2. Stack setup for ARM supervisor mode 3. External Clock Detection 4. Switch Master Clock on Main Oscillator 5. C variable initialization 6. Main oscillator frequency detection if ...

Page 77

Initialization of the DBGU serial port (115200 bauds only if OSCSEL = 1 9. Enable the user reset 10. Jump to SAM-BA Boot sequence 11. Disable the Watchdog 12. Initialization of the USB Device Port Figure ...

Page 78

SAM-BA Boot The SAM-BA boot principle is to: – Wait for USB Device enumeration. – In parallel, wait for character(s) received on the DBGU if MCK is configured to 48 – If not, the auto baud rate sequence is ...

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Table 13-4. Command • Write commands: Write a byte (O), a halfword ( word (W) to the target. – Address: Address in hexadecimal. – Value: Byte, halfword or ...

Page 80

DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to ...

Page 81

... On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. ...

Page 82

In-Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the FLASH to ...

Page 83

Hardware and Software Constraints • USB requirements: – Crystal or Input Frequencies supported by Software Auto-detection. See Table 13-7 are driven during the boot sequence. Table 13-7. Peripheral DBGU DBGU 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Table 13-2 and Table 13-3 on ...

Page 84

AT91SAM9XE128/256/512 Preliminary 84 6254C–ATARM–22-Jan-10 ...

Page 85

Fast Flash Programming Interface (FFPI) 14.1 Description The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is ...

Page 86

Table 14-1. Signal Description List (Continued) Signal Name Function Main Clock Input. This input can be tied to GND. In this XIN case, the device is clocked by the internal RC oscillator. TST Test Mode Select PGMEN0 Test Mode Select ...

Page 87

Table 14-3. DATA[15:0] 0x0011 0x0012 0x0022 0x0032 0x0042 0x0013 0x0014 0x0024 0x0015 0x0034 0x0044 0x0025 0x0054 0x0035 0x001F 0x001E 14.2.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: • Apply GND, VDDIO, VDDCORE and VDDPLL. ...

Page 88

Figure 14-2. Parallel Programming Timing, Write Sequence Table 14-4. Write Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal 6 ...

Page 89

Table 14-5. Read Handshake Step Programmer Action 1 Sets MODE and DATA signals 2 Clears NCMD signal 3 Waits for RDY low 4 Sets DATA signal in tristate 5 Clears NOE signal 6 Waits for NVALID low 7 8 Reads ...

Page 90

Table 14-6. Step n+2 n+3 ... 14.2.5.2 Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds ...

Page 91

All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 14-9. Step 1 2 14.2.5.4 Flash Lock Commands Lock bits can be ...

Page 92

General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The n GP NVM bit is active when bit n of the bit mask is set.. Table 14-13. Get GP NVM Bit Command Step 1 2 14.2.5.6 ...

Page 93

Table 14-15. Write Command (Continued) Step n+1 n+2 n+3 ... 14.2.5.8 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 14-16. Get Version Command Step 1 2 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Handshake Sequence MODE[3:0] ...

Page 94

Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a ...

Page 95

Table 14-17. Signal Description List (Continued) Signal Name Function TST Test Mode Select PGMEN0 Test Mode Select PGMEN1 Test Mode Select PGMEN2 Test Mode Select PGMEN3 Test Mode Select TCK JTAG TCK TDI JTAG Test Data In TDO JTAG Test ...

Page 96

Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these ...

Page 97

Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address ...

Page 98

Flash Full Erase Command This command is used to erase the Flash memory planes. All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 14-21. Full Erase ...

Page 99

GP NVM bits can be read using Get GPNVM Bit command (GGPB). When a bit set in the Bit Mask is returned, then the corresponding GPNVM bit is set. Table 14-25. Get General-purpose NVM Bit Command Read/Write Write Read 14.3.4.6 ...

Page 100

Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 14-28. Get Version Command Read/Write Write Read AT91SAM9XE128/256/512 Preliminary 100 DR Data GVE Version 6254C–ATARM–22-Jan-10 ...

Page 101

Reset Controller (RSTC) 15.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...

Page 102

These reset signals are asserted by the Reset Controller, either on external events or on soft- ware action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of ...

Page 103

Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven ...

Page 104

When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immedi- ately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset ...

Page 105

Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow- ers up, the POR output is ...

Page 106

When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the ...

Page 107

Figure 15-7. Brownout Reset State SLCK MCK Any Freq. brown_out or bod_reset proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) 15.3.4.5 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing ...

Page 108

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is ...

Page 109

Figure 15-9. Watchdog Reset SLCK MCK wd_fault proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 NRST (nrst_out) 15.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup ...

Page 110

RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed ...

Page 111

Reset Controller (RSTC) User Interface Table 15-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last ...

Page 112

Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFD00 Access Type: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, ...

Page 113

Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFD04 Access Type: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST ...

Page 114

Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFD08 Access Type: Read-write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on ...

Page 115

Real-time Timer (RTT) 16.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt and/or triggers an alarm on a programmed value. 16.2 Block Diagram Figure 16-1. ...

Page 116

The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...

Page 117

Real-time Timer (RTT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name RTT_MR RTT_AR RTT_VR RTT_SR Access Reset Read-write 0x0000_8000 Read-write 0xFFFF_FFFF Read-only 0x0000_0000 ...

Page 118

Real-time Timer Mode Register Register Name: RTT_MR Address: 0xFFFFFD20 Access Type: Read/Write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment ...

Page 119

Real-time Timer Alarm Register Register Name: RTT_AR Address: 0xFFFFFD24 Access Type: Read/Write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 16.4.3 Real-time Timer Value Register ...

Page 120

Real-time Timer Status Register Register Name: RTT_SR Address: 0xFFFFFD2C Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has ...

Page 121

Periodic Interval Timer (PIT) 17.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time . 17.2 Block Diagram Figure ...

Page 122

Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...

Page 123

Figure 17-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 ...

Page 124

Periodic Interval Timer (PIT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM9XE128/256/512 Preliminary 124 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only ...

Page 125

Periodic Interval Timer Mode Register Register Name: PIT_MR Address: 0xFFFFFD30 Access Type: Read/Write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter ...

Page 126

Periodic Interval Timer Status Register Register Name: PIT_SR Address: 0xFFFFFD34 Access Type: Read-only 31 30 – – – – – – – – • PITS: Periodic Interval Timer Status 0 = The Periodic ...

Page 127

Periodic Interval Timer Value Register Register Name: PIT_PIVR Address: 0xFFFFFD38 Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value ...

Page 128

Periodic Interval Timer Image Register Register Name: PIT_PIIR Address: 0xFFFFFD3C Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: ...

Page 129

Watch Dog Timer (WDT) 18.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period ...

Page 130

Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...

Page 131

Figure 18-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9XE128/256/512 Preliminary 131 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6254C–ATARM–22-Jan-10 ...

Page 132

Watchdog Timer (WDT) User Interface Table 18-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9XE128/256/512 Preliminary 132 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6254C–ATARM–22-Jan-10 ...

Page 133

Watchdog Timer Control Register Register Name: WDT_CR Address: 0xFFFFFD40 Access Type: Write-only – – – – – – • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: ...

Page 134

Watchdog Timer Mode Register Register Name: WDT_MR Address: 0xFFFFFD44 Access Type: Read-write Once 31 30 WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. ...

Page 135

WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9XE128/256/512 Preliminary 135 6254C–ATARM–22-Jan-10 ...

Page 136

Watchdog Timer Status Register Register Name: WDT_SR Address: 0xFFFFFD48 Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the ...

Page 137

Shutdown Controller (SHDWN) 19.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 19.2 Block Diagram Figure 19-1. Shutdown Controller Block Diagram Shutdown Controller SHDW_MR CPTWK0 WKMODE0 WKUP0 RTTWKEN ...

Page 138

A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter pro- viding the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that ...

Page 139

Shutdown Controller (SHDWN) User Interface Table 19-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name SHDW_CR SHDW_MR SHDW_SR Access Reset Write-only - Read-write 0x0000_0003 Read-only 0x0000_0000 139 ...

Page 140

Shutdown Control Register Register Name: SHDW_CR Address: 0xFFFFFD10 Access Type: Write-only – – – – – – • SHDW: Shutdown Command effect KEY is correct, ...

Page 141

Shutdown Mode Register Register Name: SHDW_MR Address: 0xFFFFFD14 Access Type: Read/Write 31 30 – – – – – CPTWK0 • WKMODE0: Wake-up Mode 0 WKMODE[1: ...

Page 142

Shutdown Status Register Register Name: SHDW_SR Address: 0xFFFFFD18 Access Type: Read-only 31 30 – – – – – – – – • WAKEUP0: Wake-up 0 Status wake-up event occurred on ...

Page 143

Enhanced Embedded Flash Controller (EEFC) 20.1 Description The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance. It also man- ages the programming, erasing, ...

Page 144

Figure 20-1. Embedded Flash Organization Start Address + Flash size -1 AT91SAM9XE128/256/512 Preliminary 144 Memory Plane Page 0 Start Address Page (m-1) Page (n*m-1) Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock ...

Page 145

Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in ARM and Thumb mode by means of the 128-bit wide memory interface. The Flash memory is accessible through 8-, 16- and ...

Page 146

Figure 20-3. Code Read Optimization in ARM Mode for FWS = 3 Master Clock ARM Request (32-bit) @Byte 0 Flash Access Bytes 0-15 Buffer 0 (128bits) XXX Buffer 1 (128bits) Data To ARM XXX Note: When FWS is included between ...

Page 147

Data Read Optimization The organization of the Flash in 128 bits is associated with two 128-bit prefetch buffers and one 128-bit data read buffer, thus providing maximum system performance. This buffer is added in order to start access at ...

Page 148

Flash Commands The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as program- ming the memory Flash, locking and unlocking lock regions, consecutive programming and locking and full Flash erasing, etc. Commands and read operations can ...

Page 149

Figure 20-6. Command State Chart 20.3.3.1 Getting Embedded Flash Descriptor This command allows the system to learn about the Flash organization. The system can take full advantage of this information. For instance, a device could be replaced by one with ...

Page 150

EEFC_FRR register are done after the last word of the descriptor has been returned, then the EEFC_FRR register value is 0 until the next valid command. Table 20-2. Flash Descriptor Definition Symbol FL_ID FL_SIZE FL_PAGE_SIZE FL_NB_PLANE FL_PLANE[0] ...

Page 151

Command Error: a bad keyword has been written in the EEFC_FCR register. • a Lock Error: the page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region. By ...

Page 152

The Set Lock command (SLB) and a page number to be protected are written in the Flash Command Register. • When the locking completes, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises interrupt has ...

Page 153

When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises interrupt was enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the System Controller is activated. • ...

Page 154

Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0xFFFF FA00 . Table 20-3. Register Mapping Offset Register EEFC 0x00 Flash Mode ...

Page 155

EEFC Flash Mode Register Register Name: EEFC_FMR Address: 0xFFFFFA00 Access Type: Read-write Offset: 0x60 31 30 – – – – – – – • FRDY: Ready Interrupt Enable 0: Flash Ready does not ...

Page 156

EEFC Flash Command Register Register Name: EEFC_FCR Address: 0xFFFFFA04 Access Type: Write-only Offset: 0x64 • FCMD: Flash Command This field defines the flash commands. Refer to • FARG: Flash Command Argument ...

Page 157

EEFC Flash Status Register Register Name: EEFC_FSR Address: 0xFFFFFA08 Access Type: Read-only Offset: 0x68 31 30 – – – – – – – – • FRDY: Flash Ready Status 0: The Enhanced Embedded ...

Page 158

EEFC Flash Result Register Register Name: EEFC_FRR Address: 0xFFFFFA0C Access Type: Read-only Offset: 0x6C • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If ...

Page 159

AT91SAM9XE Bus Matrix 21.1 Description Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the over- all bandwidth. Bus Matrix interconnects 6 ...

Page 160

FIXED_DEFMSTR field allows to choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description. 21.4 Arbitration The Bus Matrix provides an arbitration mechanism that allows to reduce ...

Page 161

This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). 21.4.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow ...

Page 162

For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS ...

Page 163

Bus Matrix (MATRIX) User Interface Table 21-1. Register Mapping Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration ...

Page 164

Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...MATRIX_MCFG5 Address: 0xFFFFEE00 Access: Read-write 31 30 – – – – – – – – • ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted ...

Page 165

Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...MATRIX_SCFG4 Address: 0xFFFFEE40 Access: Read-write 31 30 – – – – – • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is ...

Page 166

Bus Matrix Priority Registers For Slaves Name: MATRIX_PRS0...MATRIX_PRS4 Access: Read-write 31 30 – – – – – – – – • MxPR: Master x Priority Fixed priority of Master x for access to ...

Page 167

Chip Configuration User Interface Table 21-2. Chip Configuration User Interface Offset Register 0x0110 - 0x0118 Reserved 0x011C EBI Chip Select Assignment Register 0x0130 - 0x01FC Reserved 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name – EBI_CSA – Access Reset Value – – Read-write ...

Page 168

EBI Chip Select Assignment Register Name: EBI_CSA Access: Read-write Reset: 0x0001_0000 31 30 – – – – – – – – EBI_CS5A • EBI_CS1A: EBI Chip Select 1 Assignment 0 = EBI Chip ...

Page 169

AT91SAM9XE128/256/512 External Bus Interface 22.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM Static Memory, SDRAM and ECC Controllers are all ...

Page 170

Block Diagram 22.2.1 External Bus Interface Figure 22-1 Figure 22-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9XE128/256/512 Preliminary 170 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Static ...

Page 171

I/O Lines Description Table 22-1. EBI I/O Lines Description Name Function EBI_D0 - EBI_D31 Data Bus EBI_A0 - EBI_A25 Address Bus EBI_NWAIT External Wait Signal EBI_NCS0 - EBI_NCS7 Chip Select Lines EBI_NWR0 - EBI_NWR3 Write Signals EBI_NOE Output Enable ...

Page 172

The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 22-2 on page 172 EBI pins. Table 22-2. EBI_NWR1/NBS1/CFIOR EBI_A0/NBS0 EBI_A1/NBS2/NWR2 EBI_A[11:2] EBI_SDA10 EBI_A12 EBI_A[14:13] EBI_A[22:15] ...

Page 173

Application Example 22.4.1 Hardware Interface Table 22-3 on page 173 external devices for each Memory Controller. Table 22-3. EBI Pins and External Static Devices Connections 8-bit Static Signals: Device EBI_ Controller ...

Page 174

Table 22-4. EBI Pins and External Devices Connections Signals: EBI_ Controller D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A20 A21 A22 A23 ...

Page 175

Table 22-4. EBI Pins and External Devices Connections (Continued) Signals: EBI_ Controller CFCE2 SDCK SDCKE RAS CAS SDWE NWAIT (2) Pxx (2) Pxx (2) Pxx Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional ...

Page 176

Connection Examples Figure 22-2 Figure 22-2. EBI Connections to Memory Devices 22.5 Product Dependencies 22.5.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the ...

Page 177

ECC Controller (ECC) • a chip select assignment feature that assigns an AHB address space to the external devices • a multiplex controller circuit that shares the pins between the different Memory Controllers • programmable CompactFlash support logic ...

Page 178

I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. ...

Page 179

The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 22-6. CFCE1 and CFCE2 Truth Table Mode CFCE2 Attribute Memory NBS1 NBS1 Common ...

Page 180

Figure 22-4. CompactFlash Read/Write Control Signals Table 22-7. CompactFlash Mode Selection Mode Base Address CFOE Attribute Memory NRD Common Memory I/O Mode True IDE Mode 22.6.6.4 Multiplexing of CompactFlash Signals on EBI Pins Table 22-8 on page 180 Flash logic ...

Page 181

Table 22-9. Shared CompactFlash Interface Multiplexing Pins NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW 22.6.6.5 Application Example Figure 22-5 on page 182 CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output ...

Page 182

Figure 22-5. CompactFlash Application Example 22.6.7 NAND Flash Support External Bus Interface integrate circuitry that interfaces to NAND Flash devices. 22.6.7.1 External Bus Interface The NAND Flash Programming the EBI_CS3A field in the EBI_CSA Register in the Chip Configuration User ...

Page 183

Figure 22-6. NAND Flash Signal Multiplexing on EBI Pins 22.6.7.2 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. ...

Page 184

Figure 22-7. NAND Flash Application Example Note: AT91SAM9XE128/256/512 Preliminary 184 D[7:0] A[22:21] NCSx/NANDCS Not Connected EBI NANDOE NANDWE PIO PIO The External Bus Interface is also able to support 16-bit devices. AD[7:0] ALE CLE NAND Flash NOE NWE CE R/B ...

Page 185

Implementation Examples All the hardware configurations are given for illustration only. The user should refer to the mem- ory manufacturer web site to check device availability. 22.7.1 16-bit SDRAM Figure 22-8. Hardware Configuration 22.7.1.1 Software Configuration The following configuration ...

Page 186

SDRAM 22.7.2.1 Hardware Configuration D[0..31] A[0..14] (Not used A12 A10 A11 SDA10 SDA10 A13 BA0 BA0 BA1 BA1 A14 SDCKE SDCKE SDCK SDCK 1%6 A0 1%6 CFIOR_NBS1_NWR1 CAS CAS RAS ...

Page 187

NAND Flash Hardware Configuration 22.7.3.1 Software Configuration The following configuration has to be performed: • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register located in the ...

Page 188

NAND FLASH Hardware Configuration 22.7.4.1 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode register of the Static Memory Controller. AT91SAM9XE128/256/512 Preliminary 188 D[0..15] ...

Page 189

NOR Flash on NCS0 Hardware Configuration 22.7.5.1 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another ...

Page 190

Compact Flash 22.7.6.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 ...

Page 191

Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...

Page 192

Compact Flash True IDE 22.7.7.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 A9 A8 ...

Page 193

Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...

Page 194

AT91SAM9XE128/256/512 Preliminary 194 6254C–ATARM–22-Jan-10 ...

Page 195

Static Memory Controller (SMC) 23.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the exter- nal memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit ...

Page 196

Application Example 23.4.1 Hardware Interface Figure 23-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A2 - A25 Static Memory Controller 23.5 Product Dependencies 23.5.1 I/O Lines ...

Page 197

External Memory Mapping The SMC provides address lines, A[25:0]. This allows each chip select line to address Mbytes of memory. If the physical memory device connected on one chip select is smaller than ...

Page 198

Figure 23-3. Figure 23-4. Figure 23-5. Memory Connection for a 32-bit Data Bus AT91SAM9XE128/256/512 Preliminary 198 Memory Connection for an 8-bit Data Bus D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] Memory Connection for a 16-bit Data Bus D[15:0] A[19:2] ...

Page 199

Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. • For 16-bit devices: ...

Page 200

Figure 23-6. 23.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. shows signal multiplexing depending ...

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