LPC2420FBD208,551 NXP Semiconductors, LPC2420FBD208,551 Datasheet - Page 5

• Manufacturer Part Number: LPC2420FBD208,551
• Description: IC ARM7 MCU ROMLESS 208LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2420FBD208,551

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: EBI/EMI, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 82 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4527; 935286745551

NXP Semiconductors
5. Block diagram
LPC2420_60_5
Preliminary data sheet
Fig 1. LPC2420/2460 block diagram
6 × PWM0/PWM1
2 × CAP0/CAP1/
4 × MAT2/MAT3,
EINT3 to EINT0
power domain 2
(1) LPC2460 only.
CAP2/CAP3
1 × PCAP0,
2 × PCAP1
P0, P1, P2,
2 × MAT0,
3 × MAT1
MII/RMII
8 × AD0
ALARM
RTCX1
RTCX2
P0, P2
P0, P1
AOUT
P3, P4
VBAT
HIGH-SPEED
ETHERNET
LPC2420/2460
MAC WITH
OSCILLATOR
160 PINS
DMA
GPI/O
TOTAL
EXTERNAL INTERRUPTS
RTC
CAPTURE/COMPARE
SYSTEM CONTROL
(1)
2 kB BATTERY RAM
WATCHDOG TIMER
A/D CONVERTER
D/A CONVERTER
TIMER0/TIMER1/
TIMER2/TIMER3
LEGACY GPI/O
64 PINS TOTAL
PWM0, PWM1
AHB2
SRAM
16 kB
(1)
CONTROLLER
INTERNAL
SRAM
SRAM
64 kB
CLOCK
REAL-
TIME
BRIDGE
MASTER
PORT
TRST
AHB
Rev. 05 — 24 February 2010
ARM7TDMI-S
TMS
TEST/DEBUG
INTERFACE
TCK TDO
AHB BRIDGE
APB BRIDGE
AHB TO
TDI
AHB TO
EXTIN0
trace signals
BRIDGE
AHB
SLAVE
PORT
DBGEN
VIC
system
clock
PLL
SPI, SSP0 INTERFACE
UART0, UART2, UART3
RESET
SRAM
SSP1 INTERFACE
16 kB
CAN1
Flashless 16-bit/32-bit microcontroller
I
SD/MMC CARD
I
4 kB RAM AND DMA
2
2
HOST/OTG WITH
S INTERFACE
INTERFACE
C0, I
USB DEVICE/
XTAL2
CONTROLLER
UART1
(1)
INTERNAL RC
OSCILLATOR
AHB1
FUNCTIONS
2
GP DMA
, CAN2
C1, I
CONTROLLER
XTAL1
SYSTEM
EXTERNAL
MEMORY
2
C2
V
LPC2420/2460
(1)
DDA
V
002aad313
DD(3V3)
A[23:0]
control lines
V
port1
port2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
© NXP B.V. 2010. All rights reserved.
VREF
V
V
D[31:0]
BUS
SSA
DD(DCDC)(3V3)
, V
SSCORE
, V
5 of 79
SSIO