LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet
LPC3141FET180,551
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LPC3141/3143 Low-cost, low-power ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, and NAND flash controller Rev. 0.16 — 27 May 2010 1. General description The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 KB SRAM, ...
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... NXP Semiconductors Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB On the LPC3143 only: secure booting using an AES decryption engine from SPI flash, NAND flash, SD/MMC cards, UART, or USB. DMA controller Four 32-bit timers Watchdog timer PWM module Master/slave PCM interface ...
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... NXP Semiconductors 4. Block diagram JTAG interface LPC3141/3143 TEST/DEBUG INTERFACE ARM926EJ-S master slave INTERRUPT CONTROLLLER slave MPMC slave slave MCI SD/SDIO AHB TO APB BRIDGE 0/ ASYNC APB slave group 0 WDT SYSTEM CONTROL CGU IOCONFIG 10-bit ADC EVENT ROUTER RNG OTP APB slave group 1 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. LPC3141/3143 pinning TFBGA180 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 EBI_D_10 2 EBI_A_1_CLE 5 mGPIO7 6 mGPIO6 9 VPP 10 FFAST_IN 13 ADC10B_VDDA33 14 ADC10B_GPA1 Row B 1 EBI_D_8 2 VDDE_IOA 5 mGPIO8 6 mGPIO5 9 PWM_DATA 10 FFAST_OUT 13 ADC10B_GPA2 14 ADC10B_GPA0 Row C 1 EBI_D_7 ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row E 1 EBI_D_3 2 EBI_D_4 5 VDDE_IOA 6 mNAND_RYBN0 9 VSSA12 10 VDDA12 13 I2C_SCL1 14 I2STX_BCK1 Row F 1 EBI_D_2 2 EBI_D_1 5 VDDE_IOA 10 SCAN_TDO 13 I2SRX_WS1 14 I2SRX_BCK1 Row G 1 EBI_NCAS_BLOUT_0 2 EBI_D_0 5 VDDE_IOA 10 I2STX_WS1 13 SYSCLK_O 14 I2SRX_DATA1 Row H 1 EBI_DQM_0_NOE 2 EBI_NRAS_BLOUT_1 ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row P 1 USB_VDDA33 2 USB_DP 5 mLCD_DB_7 6 mLCD_DB_3 9 mLCD_DB_1 10 TMS 13 TRST_N 14 mUART_RTS_N Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [1] Clock Generation Unit (CGU) ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [1] USB_DM N2 SUP3 USB_VDDA12_PLL L1 SUP1 USB_VDDA33_DRV M2 SUP3 USB_VDDA33 P1 SUP3 USB_VSSA_TERM L3 - USB_GNDA N1 - USB_VSSA_REF K4 - JTAG JTAGSEL N11 SUP3 TDI K9 SUP3 TRST_N P13 SUP3 ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [1] Serial Peripheral Interface (SPI) [4] SPI_CS_OUT0 A7 SUP3 [4] SPI_SCK A8 SUP3 [4] SPI_MISO C8 SUP3 [4] SPI_MOSI B7 SUP3 [4] SPI_CS_IN B8 SUP3 Digital power supply VDDI H3; SUP1 L7; ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [1] VSSE_IOC B12; - D6; D8; D9; G11; L9; L13 LCD interface [4] mLCD_CSB K8 SUP8 [4] mLCD_E_RD L8 SUP8 [4] mLCD_RS P8 SUP8 [4] mLCD_RW_WR N9 SUP8 [4] mLCD_DB_0 N8 SUP8 [4] mLCD_DB_1 P9 SUP8 [4] mLCD_DB_2 ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [ S/digital audio output [4] mI2STX_DATA0 M13 SUP3 [4] mI2STX_BCK0 M12 SUP3 [4] mI2STX_WS0 M11 SUP3 [4] mI2STX_CLK0 N14 SUP3 [4] I2STX_DATA1 F12 SUP3 [4] I2STX_BCK1 E14 ...
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... NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [1] [4] EBI_D_5 D1 SUP4 [4] EBI_D_6 D2 SUP4 [4] EBI_D_7 C1 SUP4 [4] EBI_D_8 B1 SUP4 [4] EBI_D_9 A3 SUP4 [4] EBI_D_10 A1 SUP4 [4] EBI_D_11 C2 SUP4 [4] EBI_D_12 G3 SUP4 [4] EBI_D_13 D3 SUP4 [4] EBI_D_14 ...
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... NXP Semiconductors Table 5. Supply domains Supply Voltage range domain SUP1 1 1.3 V SUP3 2 3.6 V SUP4 1. 1.95 V (in 1.8 V mode) 2 3.6 V (in 3.3 V mode) SUP5 4 5.5 V SUP8 1. 1.95 V (in 1.8 V mode) 2 3.1 V (in 3.3 V mode) [1] When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD interface must be the same, i.e. SUP4 and SUP8 should be connected to the same rail ...
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... NXP Semiconductors 6. Functional description 6.1 ARM926EJ-S The processor embedded in the chip is the ARM926EJ- member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important. This module has the following features: • ...
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... NXP Semiconductors 6.2 Memory map LPC3141/3143 4 GB reserved 2 GB reserved NAND flash/AES buffer reserved interrupt controller reserved external SDRAM bank 0 external SRAM bank 1 external SRAM bank 0 reserved USB OTG reserved MCI/SD/SDIO reserved MPMC configuration registers APB4 domain APB3 domain APB2 domain ...
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... NXP Semiconductors • ARM926 debug access • Boundary scan • The ARM926 debug access can be permanently disabled through JTAG security bits in the One-Time Programmable memory (OTP) block. 6.4 NAND flash controller The NAND flash controller is used as a dedicated interface to NAND flash devices. ...
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... NXP Semiconductors • Support for 8-bit and 16-bit flash devices. • Support for any page size from 0.5 kB upwards. • Programmable NAND flash timing parameters. • Support for NAND devices. • Hardware AES decryption (LPC3143 only). • Error Correction Module (ECC) for MLC NAND flash support: – ...
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... NXP Semiconductors – output enable and write enable delays – extended wait • One chip select for synchronous memory and two chip selects for static memory devices. • Power-saving modes. • Dynamic memory self-refresh mode supported. • Controller support for and 8 k row address synchronous memory parts. ...
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... NXP Semiconductors The LPC3141 ROM memory has the following features: • Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and USB (DFU class) interfaces. • Supports option to perform CRC32 checking on the boot image. • Contains pre-defined MMU table (16 kB) for simple systems. ...
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... NXP Semiconductors • Implemented as two independent 96 kB memory banks 6.9 Memory Card Interface (MCI) The MCI controller interface can be used to access memory cards according to the Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well ...
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... NXP Semiconductors • Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. • Contains UTMI+ compliant transceiver (PHY). • Supports interrupts. • This module has its own, integrated DMA engine. 6.11 DMA controller The DMA controller can perform DMA transfers on the AHB without using the CPU. ...
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... NXP Semiconductors Table 9: Peripherals that support DMA Peripheral name 2 I S0/1 receive 2 I S0/1 transmit PCM interface [1] AES decryption engine is available on LPC3143 only. 6.12 Interrupt controller The interrupt controller collects interrupt requests from multiple devices, masks interrupt requests, and forwards the combined requests to the processor. The interrupt controller also provides facilities to identify the interrupt requesting devices to be served ...
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... NXP Semiconductors Multiple masters can have access to different slaves at the same time. Figure 5 gives an overview of the multi-layer AHB configuration in the LPC3141/3143. AHB masters and slaves are numbered according to their AHB port number. LPC3141_3143 Preliminary data sheet All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors ARM DMA 926EJ-S master MULTI-LAYER AHB MATRIX = master/slave connection supported by matrix (1) AES is available for LPC3143 only. Fig 5. LPC3141/3143 multi-layer AHB matrix connections LPC3141_3143 Preliminary data sheet USB-OTG AHB MASTER 3 slave 0 AHB-APB 0 BRIDGE 0 EVENT ROUTER 1 AHB-APB 0 BRIDGE 1 TIMER 0 TIMER 1 2 AHB-APB ...
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... NXP Semiconductors This module has the following features: • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). • Round-Robin priority mechanism for bus arbitration: all masters have the same priority and get bus access in their natural order. • ...
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... NXP Semiconductors 6.15 Clock Generation Unit (CGU) The clock generation unit generates all clock signals in the system and controls the reset signals for all modules. The structure of the CGU is shown in generated by the CGU belongs to one of the domains. Each clock domain is fed by a single base clock that originates from one of the available clock sources ...
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... NXP Semiconductors – Each base clock can be programmed to have any one of the clock sources as an input clock. – Fractional dividers can be used to divide a base clock by a fractional number to a lower clock frequency. – Fractional dividers support clock stretching to obtain a (near) 50% duty cycle output clock. • ...
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... NXP Semiconductors • After a reset, a register will indicate whether a reset has occurred because of a watchdog generated reset. • Watchdog timer can also be used as a normal timer in addition to the watchdog functionality (output m0). APB Fig 7. Block diagram of the Watchdog Timer 6.17 Input/Output Configuration module (IOCONFIG) The General Purpose Input/Output (GPIO) pins can be controlled through the register interface provided by the IOCONFIG module ...
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... NXP Semiconductors 6.19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake-up the system from suspend mode (with all clocks deactivated). ...
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... NXP Semiconductors 6.20 Random number generator The Random Number Generator (RNG) generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. This module has the following features: • ...
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... NXP Semiconductors The SPI/SSI-bus is a 5-wire interface, and it is suitable for low, medium, and high data rate transfers. This module has the following features: • Supports Motorola SPI frame format with a word size of 8/16 bits. • Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size of 4 bit to 16 bit. • ...
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... NXP Semiconductors – MP PCM: Multi-Protocol PCM. Configurable directional per slot. – IOM-2: Extended ISDN-Oriented modular. Double clocking physical format. • Twelve 8-bit slots in a frame with enabling control per slot. • Internal frame clock generation in master mode. • Receive and transmit DMA handshaking using a request/clear protocol. ...
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... NXP Semiconductors • Fast mode (400 kHz SCLwith 24 MHz APB clock; 325 kHz with12 MHz APB clock; 175 kHz with 6 MHz APB clock). • Interrupt support. • Supports DMA transfers (single). • Four modes of operation: – Master transmitter – Master receiver – ...
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... NXP Semiconductors Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal Description mLCD_DB_3 LCD_DB_3 EBI_A_3 mLCD_DB_4 LCD_DB_4 EBI_A_4 mLCD_DB_5 LCD_DB_5 EBI_A_5 mLCD_DB_6 LCD_DB_6 EBI_A_6 mLCD_DB_7 LCD_DB_7 EBI_A_7 mLCD_DB_8 LCD_DB_8 EBI_A_8 mLCD_DB_9 LCD_DB_9 EBI_A_9 mLCD_DB_10 LCD_DB_10 EBI_A_10 mLCD_DB_11 LCD_DB_11 EBI_A_11 ...
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... NXP Semiconductors Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal Description NAND related pin multiplexing mNAND_RYBN0 NAND_RYBN0 MCI_DAT_4 mNAND_RYBN1 NAND_RYBN1 MCI_DAT_5 mNAND_RYBN2 NAND_RYBN2 MCI_DAT_6 mNAND_RYBN3 NAND_RYBN3 MCI_DAT_7 Audio related pin multiplexing mI2STX_DATA0 I2STX_DATA0 PCM_DA mI2STX_BCK0 I2STX_BCK0 PCM_FSC mI2STX_WS0 ...
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... NXP Semiconductors control NAND_NCS_[0:3] control NAND_RYBN[0:3] NAND FLASH INTERFACE control EBI_NCAS_BLOUT_0 3 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE MPMC LCD Fig 9. Diagram of LCD and MPMC multiplexing Figure 9 only shows the signals that are involved in pad-muxing, so not all interface signals are visible. The EBI unit between the NAND flash interface and the MPMC contains an arbiter that determines which interface is muxed to the outside world ...
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... NXP Semiconductors 2. Dedicated LCD interface only: This is the LCD mode. The NAND flash supply voltage (SUP4) can be different from the LCD supply voltage (SUP8). 6.29 Timer module The LPC3141/3143 contains four fully independent timer modules, which can be used to generate interrupts after a pre-set time interval has elapsed. ...
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... NXP Semiconductors 2 6.32 AHB interface 2 The I S AHB interface has the following features: • Supports DMA transfers. • Transmit FIFO (I • Supports single 16 bit transfers to/from the left or right FIFO. • Supports single 24 bit transfers to/from the left or right FIFO. • ...
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... NXP Semiconductors 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter All digital I/O pins V input voltage i V output voltage o I output current o Temperature values T junction temperature j T storage temperature stg T ambient temperature amb ...
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... NXP Semiconductors Table 12: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter V ADC supply voltage DD(ADC) V polyfuse programming prog(pf) voltage V bus supply voltage BUS V USB analog supply DDA(USB)(3V3) voltage (3 PLL analog supply DDA(PLL)(1V2) voltage (1.2 V) Input pins and I/O pins configured as input ...
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... NXP Semiconductors Table 12: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter C input capacitance i Output pins and I/O pins configured as output V output voltage O V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I OFF-state output ...
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... NXP Semiconductors Table 12: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI USB V common-mode input i(cm) voltage V differential input i(dif) voltage [1] The parameter values specified are simulated values. ...
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... NXP Semiconductors Table 13. ADC static characteristics − ° 2 3 DD(ADC) amb Symbol Parameter V analog input voltage IA C analog input capacitance ia N ADC resolution res(ADC) E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T V offset error voltage ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 10. ADC characteristics LPC3141_3143 Preliminary data sheet ...
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... NXP Semiconductors Fig 11. Suggested 10-bit ADC interface LPC3141_3143 Preliminary data sheet LPC31XX tbd kΩ ADC SAMPLE tbd pF tbd pF V SSA All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 R vsi AD10B_GPA[0:3] V EXT 002aae136 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 8.1 Power consumption Table 14. Power consumption Symbol Parameter Conditions [1] Standby power mode I Supply current core; VDDI = 1 all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V VDDE_IOA = 1.8 V VDDE_IOB = 1.8 V VDDE_IOC = 3.3 v ADC10B_VDDA33 = 3.3 V USB_VDDA33 = 3.3 V USB_VDDA_DRV = 3 Power dissipation Total for supply domains SUP1, SUP3, SUP4, SUP8 External SDRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)) ...
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... NXP Semiconductors Table 14. Power consumption …continued Symbol Parameter Conditions External SDRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); normal mode power; without [4] dynamic clock scaling I Supply current core; VDDI = 1 all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V VDDE_IOA = 1.8 V VDDE_IOB = 1 ...
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... NXP Semiconductors Table 14. Power consumption …continued Symbol Parameter Conditions Internal SRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); normal mode power; without [6] dynamic clock scaling; MMU off I Supply current core; VDDI = 1 all other SUP1 supplies: VDDA12 = 1.2 V; USB_VDDA12_PL = 1.2 V VDDE_IOA = 1 ...
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... NXP Semiconductors 9. Dynamic characteristics 9.1 LCD controller 9.1.1 Intel 8080 mode Table 15. Dynamic characteristics: LCD controller in Intel 8080 mode pF amb Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t write enable pulse width w(en)W t read enable pulse width ...
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... NXP Semiconductors 9.1.2 Motorola 6800 mode Table 16. Dynamic characteristics: LCD controller in Motorola 6800 mode pF amb Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t rise time r t fall time f t data input set-up time su(D) t data input hold time ...
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... NXP Semiconductors 9.1.3 Serial mode Table 17. Dynamic characteristics: LCD controller serial mode pF amb Symbol Parameter T clock cycle time cy(clk) t HIGH clock pulse width w(clk)H t LOW clock pulse width w(clk)L t rise time r t fall time f t address set-up time su(A) t address hold time ...
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... NXP Semiconductors 9.2 SRAM controller Table 18. Dynamic characteristics: static external memory interface − ° ° pF +85 C, unless otherwise specified amb Symbol Parameter Common to read and write cycles t CS LOW to address valid CSLAV time Read cycle parameters t OE LOW to address valid OELAV ...
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... NXP Semiconductors EBI_NSTCS_X t CSLAV EBI_A_[15:0] EBI_DQM_0_NOE t t EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 t EBI_D_[15:0] Fig 15. External memory read access to static memory LPC3141_3143 Preliminary data sheet t OELAV t OELOEH CSLOEL BLSLAV t BLSLBLSH CSLBLSL All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 ...
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... NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_D_[15:0] EBI_NWE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 Fig 16. External memory write access to static memory LPC3141_3143 Preliminary data sheet t CSLAV t CSLDV t WELWEH t CSLWEL t WELDV t BLSLBLSH t CSLBLSL All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 t BLSHANV ...
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... NXP Semiconductors 9.3 SDRAM controller Table 19. Dynamic characteristics of SDR SDRAM memory interface − ° ° +85 C, unless otherwise specified; V amb Symbol Parameter Conditions f operating frequency oper T clock cycle time CLCL t clock LOW time CLCX t clock HIGH time CHCX t output delay time ...
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... NXP Semiconductors T CLCL t CHCX EBI_CLKOUT EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] EBI_CKE is HIGH. Fig 17. SDRAM burst read timing LPC3141_3143 Preliminary data sheet t CLCX t t d(o) h(o) READ NOP NOP NOP t d(o) t h(A) BANK su(D) h(D) COLUMN DATA n CAS DATA n+1 LATENCY = 2 All information provided in this document is subject to legal disclaimers ...
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T CLCL t CLCX t CHCX EBI_CLKOUT EBI_CKE EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] Fig 18. SDRAM bank activate and write timing t ...
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... NXP Semiconductors 9.4 NAND flash memory controller Table 20. Dynamic characteristics of the NAND Flash memory controller − ° +85 amb Symbol t REH CLS t CLH t ALS t ALH [ NANDFLASH_NAND_CLK, see LPC314x user manual. HCLK [2] See registers NandTiming1 and NandTiming2 in the LPC314x user manual. [3] Each timing parameter can be set from 7 nand_clk clock cycles to 1 nand_clk clock cycle. (A programmed zero value is treated as a one) ...
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... NXP Semiconductors 9.5 Crystal oscillator Table 21: Dynamic characteristics: crystal oscillator Symbol Parameter f oscillator frequency osc δ clock duty cycle clk C oscillator capacitance xtal t start-up time startup P drive power drive 9.6 SPI Table 22. Dynamic characteristics of SPI pins − ° ° +85 C for industrial applications ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 20. SPI master timing (CPHA = 1) Fig 21. SPI master timing (CPHA = 0) LPC3141_3143 Preliminary data sheet t SPICLK t SPISEDV DATA VALID MOSI MISO DATA VALID t SPICLK SCK (CPOL = 0) SCK (CPOL = 1) t SPISEDV DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 0.16 — ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SPI slave timing (CPHA = 1) Fig 23. SPI slave timing (CPHA = 0) 9.6.1 Texas Instruments synchronous serial mode (SSI mode) Table 23. Dynamic characteristic: SPI interface (SSI mode) − ° ° + (SUP3) over specified ranges. amb DD(IO) Symbol ...
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... NXP Semiconductors shifting edges SCK MOSI MISO Fig 24. MISO line set-up time in SSI Master mode LPC3141_3143 Preliminary data sheet t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 sampling edges 002aad326 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 2 9.7 I S-interface Table 24. Dynamic characteristics: I − ° ° +85 C for industrial applications amb Symbol Parameter common to input and output T clock cycle time cy(clk) t rise time f t fall time r output t pulse width HIGH WH t pulse width LOW WL t data output valid time ...
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... NXP Semiconductors I2SRX_SCK I2SRX_SDA I2SRX_WS 2 Fig 26. I S-bus timing (input) 2 9.8 I C-bus Table 25. Dynamic characteristic: I − ° ° [ +85 C. amb Symbol Parameter f SCL clock frequency SCL t output fall time f(o) t rise time r t fall time f t bus free time between a STOP and ...
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... NXP Semiconductors SDA t t BUF LOW SCL HD;STA Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx ( 1). 2 Fig 27. I C-bus pins clock timing LPC3141_3143 Preliminary data sheet HD;STA HIGH SU;DAT SU;STA All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 9.9 USB interface Table 26. Dynamic characteristics: USB pins (high-speed) Ω pF 1 DD(IO) Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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Application information Table 28. LCD panel connections TFBGA pin # Pin name K8 mLCD_CSB/EBI_NSTCS_0 L8 mLCD_E_RD/EBI_CKE P8 mLCD_RS/EBI_NDYCS N9 mLCD_RW_WR/EBI_DQM_1 N8 mLCD_DB_0/EBI_CLKOUT P9 mLCD_DB_1/EBI_NSTCS_1 ...
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... NXP Semiconductors 11. Marking Table 29. LPC3141/3143 Marking Line A LPC3141_3143 Preliminary data sheet Marking Description LPC3141/3143 BASIC_TYPE All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 12. Package outline TFBGA180: thin fine-pitch ball grid array package; 180 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT 1.20 0.40 0.50 max 0.80 mm nom 1.06 0.35 0.71 0.45 min 0.95 0.30 0.65 0.40 OUTLINE ...
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... NXP Semiconductors 13. Abbreviations Table 30. Abbreviations Acronym A/D ADC AES AHB AMBA APB ATA BIU CBC CE CGU CRC DFU DMA DRM DSP EBI ECC EOP ESD FIFO FPGA GF IOCONFIG IOM IrDA ISRAM ISROM JTAG LSB MCI MCU MMC MPMC OTG PCM PHY ...
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... NXP Semiconductors Table 30. Abbreviations Acronym RNG ROM SD SDHC SDIO SDR SDRAM SE0 SIR SPI SSI SysCReg TAP TDO UART USB UTMI WDT LPC3141_3143 Preliminary data sheet …continued Description Random Number Generator Read-Only Memory Secure Digital Secure Digital High Capacity Secure Digital Input Output ...
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... NXP Semiconductors 14. Revision history Table 31: Revision history Document ID Release date LPC3141_3143 v.0.16 <tbd> • Modifications: Reset state of JTAG pins and GPIO0, GPIO1, and GPIO2 pins updated in • Document template updated. • Digital I/O level for pin CLOCK_OUT corrected in • Power consumption data updated in LPC3141_3143_0.15 < ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . 13 6.1 ARM926EJ 6.2 Memory map 6.3 JTAG 6.4 NAND flash controller . . . . . . . . . . . . . . . . . . . 15 6.5 Multi-Port Memory Controller (MPMC) ...