LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 15

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
13. LPC2478 block diagram
UM10237_4
User manual
Fig 5.
6 × PWM0/PWM1
2 × CAP0/CAP1/
4 × MAT2/MAT3,
EINT3 to EINT0
power domain 2
CAP2/CAP3
1 × PCAP0,
2 × PCAP1
P0, P1, P2,
2 × MAT0,
3 × MAT1
LPC2478 block diagram
MII/RMII
8 × AD0
ALARM
RTCX1
RTCX2
P0, P2
P0, P1
AOUT
P3, P4
VBAT
HIGH-SPEED
ETHERNET
LPC2478
MAC WITH
OSCILLATOR
160 PINS
DMA
GPI/O
TOTAL
EXTERNAL INTERRUPTS
RTC
CAPTURE/COMPARE
SYSTEM CONTROL
2 kB BATTERY RAM
WATCHDOG TIMER
A/D CONVERTER
D/A CONVERTER
TIMER0/TIMER1/
TIMER2/TIMER3
LEGACY GPI/O
64 PINS TOTAL
PWM0, PWM1
AHB2
SRAM
SRAM
16 kB
64 kB
CONTROLLERS
SRAM
INTERNAL
CLOCK
REAL-
TIME
FLASH
512 kB
FLASH
BRIDGE
MASTER
PORT
TRST
AHB
Rev. 04 — 26 August 2009
ARM7TDMI-S
TMS
TEST/DEBUG
INTERFACE
TCK TDO
AHB BRIDGE
APB BRIDGE
AHB TO
TDI
AHB TO
EXTIN0
trace signals
BRIDGE
AHB
SLAVE
PORT
DBGEN
Chapter 1: LPC24XX Introductory information
VIC
system
clock
PLL
SSP0/SPI INTERFACE
UART0, UART2, UART3
SRAM
SSP1 INTERFACE
16 kB
SD/MMC CARD
I
I
RESET
4 kB RAM AND DMA
2
2
HOST/OTG WITH
CAN1, CAN2
S INTERFACE
INTERFACE
C0, I
LCD INTERFACE
USB DEVICE/
UART1
CONTROLLER
XTAL2
INTERNAL RC
OSCILLATOR
AHB1
FUNCTIONS
WITH DMA
2
C1, I
GP DMA
CONTROLLER
SYSTEM
EXTERNAL
XTAL1
MEMORY
2
C2
V
DDA
002aac805
V
DD(3V3)
UM10237
VREF
V
V
© NXP B.V. 2009. All rights reserved.
SSA
DD(DCDC)(3V3)
A[23:0]
control lines
V
port1
port2
8 × LCD control
LCDVD[23:0]
LCDCLKIN
3 × I2SRX
3 × I2STX
SCK0, SCK
MOSI0, MOSI
MISO0, MISO
SSEL0, SSEL
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1, DTR1, RTS1
RXD1, DSR1, CTS1,
DCD1, RI1
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
D[31:0]
BUS
, V
SSIO,
V
SSCORE
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