LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 207

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
6.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0xE002 8080)
6.6.2 GPIO Interrupt Enable for Rising edge register (IO0IntEnR - 0xE002 8090
6.6.3 GPIO Interrupt Enable for Falling edge register (IO0IntEnF - 0xE002 8094
6.6 GPIO interrupt registers
The following registers configure the pins of port 0 and port 2 to generate interrupts.
This read-only register indicates the presence of interrupt pending on all of the GPIO ports
that support GPIO interrupts. Only one bit per port is used.
Table 175. GPIO overall Interrupt Status register (IOIntStatus - address 0xE002 8080) bit
and IO2IntEnR - 0xE002 80B0)
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding GPIO port pin.
Table 176. GPIO Interrupt Enable for Rising edge register (IO0IntEnR - address 0xE002 8090
and IO2IntEnF - 0xE002 80B4)
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port pin.
Table 177. GPIO Interrupt Enable for Falling edge register (IO0IntEnF - address 0xE002 8094
Bit
0
1
2
31:2
Bit
31:0
Bit
31:0
Symbol
P0Int
-
P2Int
-
Symbol
P0xER
and
P2xER
Symbol
P0xEF
and
P2xEF
description
and IO2IntEnR - address 0xE002 80B0) bit description
and IO2IntEnF - address 0xE002 80B4) bit description
Value Description
0
1
-
0
1
-
Value Description
0
1
Value Description
0
1
Rev. 04 — 26 August 2009
PORT0 GPIO interrupt pending.
There are no pending interrupts on PORT0.
There is at least one pending interrupt on PORT0.
Reserved. The value read from a reserved bit is not defined.
PORT2 GPIO interrupt pending.
There are no pending interrupts on PORT2.
There is at least one pending interrupt on PORT2.
Reserved. The value read from a reserved bit is not defined.
Enable Rising edge. Bit 0 in IOxIntEnR corresponds to pin Px.0,
bit 31 in IOxIntEnR corresponds to pin Px.31.
Rising edge interrupt is disabled on the controlled pin.
Rising edge interrupt is enabled on the controlled pin.
Enable Falling edge. Bit 0 in IOxIntEnF corresponds to pin Px.0,
bit 31 in IOxIntEnF corresponds to pin Px.31.
Falling edge interrupt is disabled on the controlled pin.
Falling edge interrupt is enabled on the controlled pin.
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
UM10237
© NXP B.V. 2009. All rights reserved.
207 of 792
Reset
value
0
NA
0
NA
Reset
value
0
Reset
value
0