LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 211

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

1. How to read this chapter
2. Basic configuration
3. Introduction
UM10237_4
User manual
The Ethernet controller is avialable in parts LPC2458 and LPC2460/68/70/78.
The Ethernet controller is configured using the following registers:
The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media
Access Controller) designed to provide optimized performance through the use of DMA
hardware acceleration. Features include a generous suite of control registers, half or full
duplex operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission and
reception with Scatter-Gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem (AHB2) that is used
to access the Ethernet SRAM for Ethernet data, control, and status information. All other
AHB traffic in the LPC2400 takes place on a different AHB subsystem, effectively
separating Ethernet activity from the rest of the system. The Ethernet DMA can also
access off-chip memory via the External Memory Controller, as well as the SRAM located
on AHB1, if is not being used by the USB block. However, using memory other than the
Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and
increase the loading of AHB1.
The Ethernet block interfaces between an off-chip Ethernet PHY using the MII (Media
Independent Interface) or RMII (reduced MII) protocol. and the on-chip MIIM (Media
Independent Interface Management) serial bus.
1. Power: In the PCONP register
2. Clock: see
3. Pins: Select Ethernet pins and their modes in PINSEL2/3 and PINMODE2/3
4. Wakeup: Use the INTWAKE register
5. Interrupts: Interrupts are enabled in the VIC using the VICIntEnable register
6. Initialization: see
UM10237
Chapter 11: LPC24XX Ethernet
Rev. 04 — 26 August 2009
Remark: On reset, the Ethernet block is disabled (PCENET = 0).
(Section
Ethernet port to wake up the microcontroller from Power-down mode.
(Section
9–5).
7–3.4).
Section
Section
Rev. 04 — 26 August 2009
4–3.3.1.
11–9.5.
(Table
(Section
4–63), set bit PCENET.
4–3.4.8) to enable activity on the
© NXP B.V. 2009. All rights reserved.
User manual
211 of 792