LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 219

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
Table 186. Summary of Ethernet registers
Symbol
MAC registers
MAC1
MAC2
IPGT
IPGR
CLRT
MAXF
SUPP
TEST
MCFG
MCMD
MADR
MWTD
MRDD
MIND
-
SA0
SA1
SA2
-
Control registers
Command
Status
RxDescriptor
RxStatus
RxDescriptorNumber 0xFFE0 0110
RxProduceIndex
RxConsumeIndex
TxDescriptor
TxStatus
TxDescriptorNumber
TxProduceIndex
TxConsumeIndex
-
TSV0
TSV1
Address
0xFFE0 0000
0xFFE0 0004
0xFFE0 0008
0xFFE0 000C
0xFFE0 0010
0xFFE0 0014
0xFFE0 0018
0xFFE0 001C
0xFFE0 0020
0xFFE0 0024
0xFFE0 0028
0xFFE0 002C
0xFFE0 0030
0xFFE0 0034
0xFFE0 0038 to
0xFFE0 003F
0xFFE0 0040
0xFFE0 0044
0xFFE0 0048
0xFFE0 004C to
0xFFE0 00FC
0xFFE0 0100
0xFFE0 0104
0xFFE0 0108
0xFFE0 010C
0xFFE0 0114
0xFFE0 0118
0xFFE0 011C
0xFFE0 0120
0xFFE0 0124
0xFFE0 0128
0xFFE0 012C
0xFFE0 0130 to
0xFFE0 0154
0xFFE0 0158
0xFFE0 015C
Rev. 04 — 26 August 2009
R/W Description
R/W MAC configuration register 1.
R/W MAC configuration register 2.
R/W Back-to-Back Inter-Packet-Gap register.
R/W Non Back-to-Back Inter-Packet-Gap register.
R/W Collision window / Retry register.
R/W Maximum Frame register.
R/W PHY Support register.
R/W Test register.
R/W MII Mgmt Configuration register.
R/W MII Mgmt Command register.
R/W MII Mgmt Address register.
WO MII Mgmt Write Data register.
RO
RO
-
R/W Station Address 0 register.
R/W Station Address 1 register.
R/W Station Address 2 register.
-
R/W Command register.
RO
R/W Receive descriptor base address register.
R/W Receive status base address register.
R/W Receive number of descriptors register.
RO
R/W Receive consume index register.
R/W Transmit descriptor base address register.
R/W Transmit status base address register.
R/W Transmit number of descriptors register.
R/W Transmit produce index register.
RO
-
RO
RO
MII Mgmt Read Data register.
MII Mgmt Indicators register.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Status register.
Receive produce index register.
Transmit consume index register.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit
is not defined.
Transmit status vector 0 register.
Transmit status vector 1 register.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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