LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 221

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 187. MAC Configuration register 1 (MAC1 - address 0xFFE0 0000) bit description
Table 188. MAC Configuration register 2 (MAC2 - address 0xFFE0 0004) bit description
UM10237_4
User manual
Bit
0
1
2
3
4
7:5
8
9
10
11
13:12 -
14
15
31:16 -
Bit
0
1
2
Symbol
RECEIVE ENABLE
PASS ALL RECEIVE
FRAMES
RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control
TX FLOW CONTROL When enabled (set to ’1’), PAUSE Flow Control frames are allowed to be
LOOPBACK
-
RESET TX
RESET MCS / TX
RESET RX
RESET MCS / RX
SIMULATION RESET Setting this bit will cause a reset to the random number generator within the
SOFT RESET
Symbol
FULL-DUPLEX
FRAME LENGTH
CHECKING
HUGE FRAME
ENABLE
7.1.1 MAC Configuration Register 1 (MAC1 - 0xFFE0 0000)
7.1.2 MAC Configuration Register 2 (MAC2 - 0xFFE0 0004)
The MAC configuration register 1 (MAC1) has an address of 0xFFE0 0000. Its bit
definition is shown in
The MAC configuration register 2 (MAC2) has an address of 0xFFE0 0004. Its bit
definition is shown in
Function
When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled,
the MAC operates in Half-Duplex mode.
When enabled (set to ’1’), both transmit and receive frame lengths are compared to
the Length/Type field. If the Length/Type field represents a length then the check is
performed. Mismatches are reported in the StatusInfo word for each received frame.
When enabled (set to ’1’), frames of any length are transmitted and received.
Function
Set this to allow receive frames to be received. Internally the MAC synchronizes
this control bit to the incoming receive stream.
When enabled (set to ’1’), the MAC will pass all frames regardless of type (normal
vs. Control). When disabled, the MAC does not pass valid Control frames.
frames. When disabled, received PAUSE Flow Control frames are ignored.
transmitted. When disabled, Flow Control frames are blocked.
Setting this bit will cause the MAC Transmit interface to be looped back to the MAC
Receive interface. Clearing this bit results in normal operation.
Unused
Setting this bit will put the Transmit Function logic in reset.
Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic
implements flow control.
Setting this bit will put the Ethernet receive logic in reset.
Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic
implements flow control.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Transmit Function.
Setting this bit will put all modules within the MAC in reset except the Host
Interface.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Table
Table
Rev. 04 — 26 August 2009
11–187.
11–188.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
221 of 792
Reset
value
0
0
0
0
0
0x0
0
0
0
0x0
0x0
0
1
0x0
Reset
value
0
0
0