LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 222

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 188. MAC Configuration register 2 (MAC2 - address 0xFFE0 0004) bit description
Table 189. Pad operation
UM10237_4
User manual
Bit
3
4
5
6
7
8
9
11:10
12
13
14
31:15
Type
Any
Any
Any
Any
Symbol
DELAYED CRC
CRC ENABLE
PAD / CRC ENABLE
VLAN PAD ENABLE
AUTO DETECT PAD
ENABLE
PURE PREAMBLE
ENFORCEMENT
LONG PREAMBLE
ENFORCEMENT
-
NO BACKOFF
BACK PRESSURE /
NO BACKOFF
EXCESS DEFER
-
Auto detect
pad enable
MAC2 [7]
x
0
x
1
VLAN pad
enable
MAC2 [6]
x
0
1
0
Function
This bit determines the number of bytes, if any, of proprietary header information
that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored
by the CRC function) are added. When 0, there is no proprietary header.
Set this bit to append a CRC to every frame whether padding was required or not.
Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the
MAC contain a CRC.
Set this bit to have the MAC pad all short frames. Clear this bit if frames presented
to the MAC have a valid length. This bit is used in conjunction with AUTO PAD
ENABLE and VLAN PAD ENABLE. See
the pad function.
Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid
CRC. Consult
padding features.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
Set this bit to cause the MAC to automatically detect the type of frame, either tagged
or un-tagged, by comparing the two octets following the source address with
0x8100 (VLAN Protocol ID) and pad accordingly.
provides a description of the pad function based on the configuration of this register.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
When enabled (set to ’1’), the MAC will verify the content of the preamble to ensure
it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded.
When disabled, no preamble checking is performed.
When enabled (set to ’1’), the MAC only allows receive packets which contain
preamble fields less than 12 bytes in length. When disabled, the MAC allows any
length preamble as per the Standard.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
When enabled (set to ’1’), the MAC will immediately retransmit following a collision
rather than using the Binary Exponential Backoff algorithm as specified in the
Standard.
When enabled (set to ’1’), after the MAC incidentally causes a collision during back
pressure, it will immediately retransmit without backoff, reducing the chance of
further collisions and ensuring transmit packets get sent.
When enabled (set to ’1’) the MAC will defer to carrier indefinitely as per the
Standard. When disabled, the MAC will abort when the excessive deferral limit is
reached.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Pad/CRC
enable
MAC2 [5]
0
1
1
1
Table 11–189
Rev. 04 — 26 August 2009
Action
No pad or CRC check
Pad to 60 bytes, append CRC
Pad to 64 bytes, append CRC
If untagged, pad to 60 bytes and append CRC. If VLAN tagged: pad to
64 bytes and append CRC.
- Pad Operation for more information on the various
Table 11–189
Table 11–189
- Pad Operation for details on
Chapter 11: LPC24XX Ethernet
- Pad Operation
UM10237
© NXP B.V. 2009. All rights reserved.
222 of 792
Reset
value
0
0
0
0
0
0
0
0x0
0
0
0
0x0