LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 238

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
7.3.4 Hash Filter Table LSBs Register (HashFilterL - 0xFFE0 0210)
7.3.5 Hash Filter Table MSBs Register (HashFilterH - 0xFFE0 0214)
7.4.1 Interrupt Status Register (IntStatus - 0xFFE0 0FE0)
7.4 Module control register definitions
Table 225. Receive Filter WoL Clear register (RxFilterWoLClear - address 0xFFE0 0208) bit
The bits in this register are write-only; writing resets the corresponding bits in the
RxFilterWoLStatus register.
The Hash Filter table LSBs register (HashFilterL) has an address of 0xFFE0 0210.
Table 11–226
found in
Table 226. Hash Filter Table LSBs register (HashFilterL - address 0xFFE0 0210) bit
The Hash Filter table MSBs register (HashFilterH) has an address of 0xFFE0 0214.
Table 11–227
found in
Table 227. Hash Filter MSBs register (HashFilterH - address 0xFFE0 0214) bit description
The Interrupt Status register (IntStatus) is a Read Only register with an address of
0xFFE0 0FE0. The interrupt status register bit definition is shown in
that all bits are flip-flops with an asynchronous set in order to be able to generate
interrupts if there are wake-up events while clocks are disabled.
Bit
0
1
2
3
4
5
6
7
8
31:9 -
Bit
31:0
Bit
31:0
Symbol
AcceptUnicastWoLClr
AcceptBroadcastWoLClr
AcceptMulticastWoLClr
AcceptUnicastHashWoLClr
AcceptMulticastHashWoLClr
AcceptPerfectWoLClr
-
RxFilterWoLClr
MagicPacketWoLClr
Symbol
HashFilterL
Symbol
HashFilterH
Section 11–9.13 “Receive filtering” on page
Section 11–9.13 “Receive filtering” on page
description
description
lists the bit definitions of the register. Details of Hash filter table use can be
lists the bit definitions of the register. Details of Hash filter table use can be
Rev. 04 — 26 August 2009
Function
Bit 31:0 of the imperfect filter hash table for receive
filtering.
Function
Bit 63:32 of the imperfect filter hash table for receive
filtering.
Function
When a ’1’ is written to one of these bits (0 to 5), the
corresponding status bit in the RxFilterWoLStatus
register is cleared.
Unused
When a ’1’ is written to one of these bits (7 and/or 8),
the corresponding status bit in the RxFilterWoLStatus
register is cleared.
Unused
268.
268.
Chapter 11: LPC24XX Ethernet
Table
UM10237
© NXP B.V. 2009. All rights reserved.
11–228. Note
238 of 792
0
Reset
value
0
0
0
0
0
0x0
0
0
0x0
Reset
value
0x0
Reset
value
0x0