LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 249

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
The DMA managers work with arrays of frame descriptors and statuses that are stored in
memory. The descriptors and statuses act as an interface between the Ethernet hardware
and the device driver software. There is one descriptor array for receive frames and one
descriptor array for transmit frames. Using buffering for frame descriptors, the memory
traffic and memory bandwidth utilization of descriptors can be kept small.
Each frame descriptor contains two 32 bit fields: the first field is a pointer to a data buffer
containing a frame or a fragment, whereas the second field is a control word related to
that frame or fragment.
The software driver must write the base addresses of the descriptor and status arrays in
the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number of
descriptors/statuses in each array must be written in the
TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in an
array corresponds to the number of statuses in the associated status array.
Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be
aligned on a 4 byte (32bit)address boundary, while the receive status array must be
aligned on a 8 byte (64bit) address boundary.
Ownership of descriptors
Both device driver software and Ethernet hardware can read and write the descriptor
arrays at the same time in order to produce and consume descriptors. Arbitration on the
AHB bus gives priority to the DMA hardware in the case of simultaneous requests. A
descriptor is "owned" either by the device driver or by the Ethernet hardware. Only the
owner of a descriptor reads or writes its value. Typically, the sequence of use and
ownership of descriptors and statuses is as follows: a descriptor is owned and set up by
the device driver; ownership of the descriptor/status is passed by the device driver to the
Ethernet block, which reads the descriptor and writes information to the status field; the
Ethernet block passes ownership of the descriptor back to the device driver, which uses
the status information and then recycles the descriptor to be used for another frame.
Software must pre-allocate the memory used to hold the descriptor arrays.
Software can hand over ownership of descriptors and statuses to the hardware by
incrementing (and wrapping if on the array boundary) the
TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors and
status to software by updating the TxConsumeIndex/ RxProduceIndex registers.
After handing over a descriptor to the receive and transmit DMA hardware, device driver
software should not modify the descriptor or reclaim the descriptor by decrementing the
TxProduceIndex/ RxConsumeIndex registers because descriptors may have been
prefetched by the hardware. In this case the device driver software will have to wait until
the frame has been transmitted or the device driver has to soft-reset the transmit and/or
receive datapaths which will also reset the descriptor arrays.
Sequential order with wrap-around
When descriptors are read from and statuses are written to the arrays, this is done in
sequential order with wrap-around. Sequential order means that when the Ethernet block
has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is
the one at the next higher, adjacent memory address. Wrap around means that when the
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
249 of 792