LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 268

IC ARM7 MCU FLASH 512K 208TFBGA

LPC2468FET208,551

Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2468FET208,551

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2468FET208,551
Manufacturer:
NXP
Quantity:
6 174
Part Number:
LPC2468FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
UM10237_4
User manual
9.13 Receive filtering
In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent
until TxFlowControl is deasserted. If the medium is idle, the Ethernet block begins
transmitting preamble, which raises carrier sense causing all other stations to defer. In the
event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the
collision. The colliding station backs off and then defers to the backpressure. If during
backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame
sent and then the backpressure resumed. If TxFlowControl is asserted for longer than
3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending
preamble for several byte times to avoid the jabber limit.
Features of receive filtering
The Ethernet MAC has several receive packet filtering functions that can be configured
from the software driver:
The filtering functions can be logically combined to create complex filtering functions.
Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; a
promiscuous mode allows all packets to be passed to software.
Overview
The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet
destination address in the frame. This capability greatly reduces the load on the host
system, because Ethernet frames that are addressed to other stations would otherwise
need to be inspected and rejected by the device driver software, using up bandwidth,
memory space, and host CPU time. Address filtering can be implemented using the
perfect address filter or the (imperfect) hash filter. The latter produces a 6 bits hash code
which can be used as an index into a 64 entry programmable hash table.
depicts a functional view of the receive filter.
At the top of the diagram the Ethernet receive frame enters the filters. Each filter is
controlled by signals from control registers; each filter produces a ‘Ready’ output and a
‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering
then it will assert its Ready output; if the filter finds a matching frame it will assert the
Match output along with the Ready output. The results of the filters are combined by logic
functions into a single RxAbort output. If the RxAbort output is asserted, the frame does
not need to be received.
In order to reduce memory traffic, the receive datapath has a buffer of 68 bytes. The
Ethernet MAC will only start writing a frame to memory after 68 byte delays. If the RxAbort
signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and
removed from the buffer and not stored to memory at all, not using up receive descriptors,
etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due to
reception of a Magic Packet), part of the frame is already written to memory and the
Perfect address filter: allows packets with a perfectly matching station address to be
identified and passed to the software driver.
Hash table filter: allows imperfect filtering of packets based on the station address.
Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or
broadcast packets.
Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt.
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
Figure 11–33
268 of 792

Related parts for LPC2468FET208,551