LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 271

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
9.15 Wake-up on LAN
Overview
The Ethernet block supports power management with remote wake-up over LAN. The
host system can be powered down, even including part of the Ethernet block itself, while
the Ethernet block continues to listen to packets on the LAN. Appropriately formed
packets can be received and recognized by the Ethernet block and used to trigger the
host system to wake up from its power-down state.
Wake-up of the system takes effect through an interrupt. When a wake-up event is
detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger
an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This
interrupt should be used by system power management logic to wake up the system.
While in a power-down state the packet that generates a Wake-up on LAN event is lost.
There are two ways in which Ethernet packets can trigger wake-up events: generic
Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for
Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if the
triggering packet has a valid CRC.
signal.
The RxFilterWoLStatus register can be read by the software to inspect the reason for a
Wake-up event. Before going to power-down the power management software should
clear the register by writing the RxFilterWolClear register.
NOTE: when entering in power-down mode, a receive frame might be not entirely stored
into the Rx buffer. In this situation, after turning exiting power-down mode, the next
receive frame is corrupted due to the data of the previous frame being added in front of
the last received frame. Software drivers have to reset the receive datapath just after
exiting power-down mode.
The following subsections describe the two Wake-up on LAN mechanisms.
Filtering for WoL
The receive filter functionality can be used to generate Wake-up on LAN events. If the
RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt
bit of the IntStatus register if a frame is received that passes the filter. The interrupt will
only be generated if the CRC of the frame is correct.
Magic Packet WoL
The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet
technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely
intended for wake-up purposes. This packet can be received, analyzed and recognized by
the Ethernet block and used to trigger a wake-up event.
A Magic Packet is a packet that contains in its data portion the station address repeated
16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization
bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in the
data portion of the packet. The whole packet must be a well-formed Ethernet frame.
Rev. 04 — 26 August 2009
Figure 11–33
shows the generation of the wake-up
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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