LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 272

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
9.16 Enabling and disabling receive and transmit
The magic packet detection unit analyzes the Ethernet packets, extracts the packet
address and checks the payload for the Magic Packet pattern. The address from the
packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic
packet only sets the wake-up interrupt status bit if the packet passes the receive filter as
illustrated in
filter result to produce the result.
Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl
register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the
RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all
packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets
is more strict.
When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register,
the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the
bit writing a 1 to the corresponding bit of the RxFilterWoLClear register.
Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55
0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet):
<DESTINATION> <SOURCE> <MISC>
FF FF FF FF FF FF
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66
<MISC> <CRC>
Enabling and disabling reception
After reset, the receive function of the Ethernet block is disabled. The receive function can
be enabled by the device driver setting the RxEnable bit in the Command register and the
“RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order).
The status of the receive datapath can be monitored by the device driver by reading the
RxStatus bit of the Status register.
generation of the RxStatus bit.
Figure
11–33: the result of the receive filter is ANDed with the magic packet
Rev. 04 — 26 August 2009
Figure 11–34
illustrates the state machine for the
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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