LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 29
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC2468FET208,551
Manufacturer:
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Quantity:
6 174
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Part Number:
LPC2468FET208,551
Manufacturer:
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UM10237_4
User manual
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt),
corresponding bit in the EXTINT register must be cleared! For details see
3–3.1.3 “External Interrupt Mode register (EXTMODE - 0xE01F C148)”
3–3.1.4 “External Interrupt Polarity register (EXTPOLAR - 0xE01F
For example, if a system wakes up from power-down using low level on external interrupt
0 pin, its post-wakeup code must reset EINT0 bit in order to allow future entry into the
power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
More details on power-down mode will be discussed in the following chapters.
Table 25.
[1]
Bit Symbol Description
0
1
2
3
7:4 -
Example: If the EINTx is selected to be low level sensitive and low level is present on corresponding pin,
this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high.
EINT0
EINT1
EINT2
EINT3
External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description
In level-sensitive mode, this bit is set if the EINT0 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT0 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
In level-sensitive mode, this bit is set if the EINT1 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT1 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
In level-sensitive mode, this bit is set if the EINT2 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT2 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
In level-sensitive mode, this bit is set if the EINT3 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT3 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
[1]
[1]
[1]
[1]
Chapter 3: LPC24XX System control
C14C)”.
UM10237
© NXP B.V. 2009. All rights reserved.
and
Section
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29 of 792
Reset
value
0
0
0
0
NA
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