LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 299

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 256. Buffer to pixel mapping for 64 x 64 pixel cursor format
UM10237_4
User manual
Data bits
5:4
3:2
1:0
(1, 0)
(2, 0)
(3, 0)
0
6.6 Gray scaler
6.7 Upper and lower panel formatters
(17, 0)
(18, 0)
(19, 0)
Cursor pixel encoding
Each pixel of the cursor requires two bits of information. These are interpreted as Color0,
Color1, Transparent, and Transparent inverted.
In the coding scheme, bit 1 selects between color and transparent (AND mask) and bit 0
selects variant (XOR mask).
Table 12–257
Table 257. Pixel encoding
A patented gray scale algorithm drives monochrome and color STN panels. This provides
15 gray scales for monochrome displays. For STN color displays, the three color
components (RGB) are gray scaled simultaneously. This results in 3375 (15x15x15)
colors being available. The gray scaler transforms each 4-bit gray value into a sequence
of activity-per-pixel over several frames, relying to some degree on the display
characteristics, to give the representation of gray scales and color.
Formatters are used in STN mode to convert the gray scaler output to a parallel format as
required by the display. For monochrome displays, this is either 4 or 8 bits wide, and for
color displays, it is 8 bits wide.
worth of data in a repeating sequence.
Value
00
01
10
11
4
(33, 0)
(34, 0)
(35, 0)
Description
Color0.
The cursor color is displayed according to the Red-Green-Blue (RGB) value
programmed into the CRSR_PAL0 register.
Color1.
The cursor color is displayed according to the RGB value programmed into the
CRSR_PAL1 register.
Transparent.
The cursor pixel is transparent, so is displayed unchanged. This enables the visible
cursor to assume shapes that are not square.
Transparent inverted.
The cursor pixel assumes the complementary color of the frame pixel that is displayed.
This can be used to ensure that the cursor is visible regardless of the color of the
frame buffer image.
8
shows the pixel encoding bit assignments.
(49, 0)
(50, 0)
(51, 0)
12
Rev. 04 — 26 August 2009
Offset into cursor memory
(16 * y)
Table 12–258
(1, y)
(2, y)
(3, y)
(16 * y) +4
(17, y)
(18, y)
(19, y)
shows a color display driven with 2 2/3 pixels
Chapter 12: LPC24XX LCD controller
(16 * y) + 8
(33, y)
(34, y)
(35, y)
(16 * y) + 12
(49, y)
(50, y)
(51, y)
UM10237
© NXP B.V. 2009. All rights reserved.
(49, 63)
(50, 63)
(51, 63)
299 of 792
FC