LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 314

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
7.10 Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020)
Table 268. Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
The LCD_INTRAW register contains status flags for various LCD controller events. These
flags can generate an interrupts if enabled by mask bits in the LCD_INTMSK register.
The contents of LCD_INTRAW register are described in
Table 269. Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020)
Bits
2
1
0
Bits
31:5
4
3
2
1
0
Function
LNBUIM
FUFIM
reserved
Function
reserved
BERRAW
VCompRIS
LNBURIS
FUFRIS
reserved
Rev. 04 — 26 August 2009
Description
LCD next base address update interrupt enable.
0: The base address update interrupt is disabled.
1: Interrupt will be generated when the LCD base address
registers have been updated from the next address registers.
FIFO underflow interrupt enable.
0: The FIFO underflow interrupt is disabled.
1: Interrupt will be generated when the FIFO underflows.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
AHB master bus error raw interrupt status.
Set when the AHB master interface receives a bus error
response from a slave.
Generates an interrupt if the BERIM bit in the LCD_INTMSK
register is set.
Vertical compare raw interrupt status.
Set when one of the four vertical regions is reached, as selected
by the LcdVComp bits in the LCD_CTRL register.
Generates an interrupt if the VCompIM bit in the LCD_INTMSK
register is set.
LCD next address base update raw interrupt status.
Mode dependent. Set when the current base address registers
have been successfully updated by the next address registers.
Signifies that a new next address can be loaded if double
buffering is in use.
Generates an interrupt if the LNBUIM bit in the LCD_INTMSK
register is set.
FIFO underflow raw interrupt status.
Set when either the upper or lower DMA FIFOs have been read
accessed when empty causing an underflow condition to occur.
Generates an interrupt if the FUFIM bit in the LCD_INTMSK
register is set.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 12: LPC24XX LCD controller
Table
12–269.
UM10237
© NXP B.V. 2009. All rights reserved.
314 of 792
Reset
value
0x0
0x0
-
Reset
value
-
0x0
0x0
0x0
-