LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 32

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
On the assertion of any of reset sources (POR, BOD reset, External reset and Watchdog
reset), the following two sequences start simultaneously:
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 3–11
processor status when the LPC2400 starts up after reset. For the start-up sequence of the
main oscillator if enabled by the user code, see
USB need_clk wakeup
1. After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock
2. After IRC-start-up time (maximum of 60 μs on power-up), IRC provides stable clock
Ethernet MAC wakeup
Fig 10. Reset block diagram including the wakeup timer
GPIO0 port wakeup
GPIO2 port wakeup
output, the reset signal is latched and synchronized on the IRC clock. The 2-bit IRC
wakeup timer starts counting when the synchronized reset is de-asserted. The boot
code in the ROM starts when the 2-bit IRC wakeup timer times out. The boot code
performs the boot tasks and may jump to the flash. If the flash is not ready to access,
the MAM will insert wait cycles until the flash is ready.
output, the reset signal is synchronized on the IRC clock. The flash wakeup-timer
(9-bit) starts counting when the synchronized reset is de-asserted. The flash
wakeup-timer generates the 100 μs flash start-up time. Once it times out, the flash
initialization sequence is started, which takes about 250 cycles. When it’s done, the
MAM will be granted access to the flash.
external
reset
EINT0 wakeup
EINT1 wakeup
EINT2 wakeup
EINT3 wakeup
watchdog
CAN wakeup
power-
BOD wakeup
RTC wakeup
down
reset
POR
BOD
shows an example of the relationship between the RESET, the IRC, and the
Rev. 04 — 26 August 2009
C
S
Q
internal RC
oscillator
Section 4–2.2 “Main
Chapter 3: LPC24XX System control
from APB
write “1”
START
WAKEUP TIMER
reset
COUNT 2
Reset to the
on-chip circuitry
Reset to
PCON.PD
oscillator”.
UM10237
n
© NXP B.V. 2009. All rights reserved.
APB read of
PDBIT
in PCON
F
to other
blocks
OSC
C
S
32 of 792
Q