LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 341

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 299. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description
Table 300. USB Device Interrupt Enable register (USBDevIntEn - address 0xFFE0 C204) bit allocation
Reset value: 0x0000 0000
Table 301. USB Device Interrupt Enable register (USBDevIntEn - address 0xFFE0 C204) bit description
UM10237_4
User manual
Bit
6
7
8
9
31:10 -
Bit
31:0
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
RxENDPKT The current packet in the endpoint buffer is transferred to the CPU.
TxENDPKT
EP_RLZED
ERR_INT
Symbol
See
USBDevIntEn
bit allocation
table above
TxENDPKT
9.3.3 USB Device Interrupt Enable register (USBDevIntEn - 0xFFE0 C204)
9.3.4 USB Device Interrupt Clear register (USBDevIntClr - 0xFFE0 C208)
31
23
15
7
-
-
-
Description
The number of data bytes transferred to the endpoint buffer equals the number of
bytes programmed in the TxPacket length register (USBTxPLen).
Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize
register (USBMaxPSize) is updated and the corresponding operation is completed.
Error Interrupt. Any bus error interrupt from the USB device. Refer to
“Read Error Status (Command: 0xFB, Data: read 1 byte)” on page 368
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Value
0
1
Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to
generate an interrupt on one of the interrupt lines when set. By default, the interrupt is
routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME
interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of
USBDevIntPri. USBDevIntEn is a read/write register.
Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a
zero has no effect.
Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding
endpoint interrupts in USBEpIntSt should be cleared.
USBDevIntClr is a write only register.
ENDPKT
Rx
30
22
14
6
Description
No interrupt is generated.
An interrupt will be generated when the corresponding bit in the Device
Interrupt Status (USBDevIntSt) register
the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally,
either the EP_FAST or FRAME interrupt may be routed to the
USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-
-
-
CDFULL
29
21
13
5
-
-
-
Rev. 04 — 26 August 2009
CCEMPTY
28
20
12
4
-
-
-
DEV_STAT
Chapter 13: LPC24XX USB device controller
(Table
27
19
11
3
-
-
-
13–298) is set. By default,
EP_SLOW
26
18
10
2
-
-
-
Section 13–11.9
ERR_INT
EP_FAST
25
17
UM10237
9
1
-
-
© NXP B.V. 2009. All rights reserved.
Reset value
0
0
0
0
NA
Reset value
0
EP_RLZED
FRAME
341 of 792
24
16
8
0
-
-