LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 345

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 309. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit allocation
Reset value: 0x0000 0000
Table 310. USB Endpoint Interrupt Enable register (USBEpIntEn - address 0xFFE0 C234) bit description
Table 311. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xFFE0 C238) bit allocation
Reset value: 0x0000 0000
UM10237_4
User manual
Bit
31:0
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
See
USBEpIntEn
bit allocation
table above
EP15TX
9.4.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0xFFE0 C238)
EP15TX
EP11TX
EP11TX
EP7TX
EP3TX
31
23
15
31
23
7
Value
0
1
Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt
command to be executed
zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the
CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the
CDFULL bit is set, USBCmdData contains the status of the endpoint, and the
corresponding bit in USBEpIntSt is cleared.
Notes:
Each physical endpoint has its own reserved bit in this register. The bit field definition is
the same as that of USBEpIntSt shown in
register.
•
•
•
When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be
set to ensure the corresponding interrupt has been cleared before proceeding.
While setting multiple bits in USBEpIntClr simultaneously is possible, it is not
recommended; only the status of the endpoint corresponding to the least significant
interrupt bit cleared will be available at the end of the operation.
Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly
invoked using the SIE command registers, but using USBEpIntClr is recommended
because of its ease of use.
EP15RX
EP15RX
EP11RX
EP11RX
EP7RX
EP3RX
30
22
14
30
22
6
Description
The corresponding bit in USBDMARSt is set when an interrupt occurs for
this endpoint.
The corresponding bit in USBEpIntSt is set when an interrupt occurs
for this endpoint.
EP14TX
EP10TX
EP14TX
EP10TX
EP6TX
EP2TX
29
21
13
29
21
5
Rev. 04 — 26 August 2009
Implies Slave mode for this endpoint.
(Table
EP14RX
EP10RX
EP14RX
EP10RX
EP6RX
EP2RX
28
20
12
28
20
13–354) for the corresponding physical endpoint. Writing
4
EP13TX
Table 13–307
EP13TX
Chapter 13: LPC24XX USB device controller
EP9TX
EP5TX
EP9TX
EP1TX
27
19
27
19
11
3
EP13RX
EP13RX
EP9RX
EP5RX
EP1RX
EP9RX
. USBEpIntClr is a write only
26
18
10
26
18
2
EP12TX
EP12TX
EP8TX
EP4TX
EP0TX
EP8TX
25
17
25
17
UM10237
9
1
© NXP B.V. 2009. All rights reserved.
Reset value
0
EP12RX
EP12RX
EP8RX
EP8RX
EP4RX
EP0RX
345 of 792
24
16
24
16
8
0