LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 360

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
10. Interrupt handling
UM10237_4
User manual
9.8.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0xFFE0 C2C0)
Table 345. USB System Error Interrupt Clear register (USBSysErrIntClr - address
Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntSet is a write only register.
Table 346. USB System Error Interrupt Set register (USBSysErrIntSet - address 0xFFE0
This section describes how an interrupt event on any of the endpoints is routed to the
Vectored Interrupt Controller (VIC). For a diagram showing interrupt event handling, see
Figure
All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet has been succesfully transmitted or when a NAK
signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see
Section
The interrupt handling is different for Slave and DMA mode.
Slave mode
If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the
USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For
non-isochronous endpoints, all endpoint interrupt events are divided into two types by the
corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint
interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in
the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the
EP_SLOW bit in USBDevIntSt.
For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms.
The USBDevIntSt register holds the status of all endpoint interrupt events as well as the
status of various other interrupts (see
enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt
Bit
31:0
Bit
31:0 EPxx
Symbol
Symbol
EPxx
13–47.
13–11.3. For isochronous endpoints, a frame interrupt is generated every 1 ms.
0xFFE0 C2BC) bit description
C2C0) bit description
Value
0
1
Value
0
1
Rev. 04 — 26 August 2009
Description
Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
No effect.
Clear the EPxx System Error Interrupt request in the
USBSysErrIntSt register.
Description
Set endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0
No effect.
Set the EPxx System Error Interrupt request in the
USBSysErrIntSt register.
Section
Chapter 13: LPC24XX USB device controller
13–9.3.2). By default, all interrupts (if
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
value
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Reset
value