LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 373

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
13. Slave mode operation
UM10237_4
User manual
13.1 Interrupt generation
13.2 Data transfer for OUT endpoints
10. Install USB interrupt handler in the VIC by writing its address to the corresponding
11. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address
12. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status
The configuration of the endpoints varies depending on the software application. By
default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional
endpoints are enabled and configured by software after a SET_CONFIGURATION or
SET_INTERFACE device request is received from the host.
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface.
In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated
in response to an endpoint interrupt. Endpoint interrupts are enabled using the
USBEpIntEn register, and are observable in the USBEpIntSt register.
All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a
packet without an error. All non-isochronous IN endpoints generate an interrupt when a
packet is successfully transmitted, or when a NAK handshake is sent on the bus and the
interrupt on NAK feature is enabled.
For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in
USBDevIntSt) occurs.
When the software wants to read the data from an endpoint buffer it should set the
RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the
USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register,
and set the PKT_RDY bit
Software can now start reading the data from the USBRxData register
When the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is
set in the USBDevSt register. Software now issues a Clear Buffer (refer to
command. The endpoint is now ready to accept the next packet. For OUT isochronous
– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0
– Enable the desired endpoints for DMA operation using USBEpDMAEn.
– Set EOT, DDR, and ERR bits in USBDMAIntEn.
VICVectAddr register and enabling the USB interrupt in the VICIntEnable register.
command. A bus reset will also cause this to happen.
command.
USBSysErrIntClr.
0000).
Rev. 04 — 26 August 2009
(Table 13–322
).
Chapter 13: LPC24XX USB device controller
UM10237
(Table
© NXP B.V. 2009. All rights reserved.
Table
13–321).
13–356)
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