LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 39

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
Table 38.
[1]
4. Brown-out detection
UM10237_4
User manual
Bit
5
6
31:7 -
The state of this bit is preserved through a software reset, and only a POR or a BOD event will reset it to its default value.
Symbol
OSCEN
OSCSTAT
System Controls and Status register (SCS - address 0xE01F C1A0) bit description
Value Description
0
1
0
1
-
The LPC2400 includes 2-stage monitoring of the voltage on the V
voltage falls below 2.95 V, the Brown-Out Detector (BOD) asserts an interrupt signal to
the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt
Enable Register in the VIC (see
0xFFFF
by reading the Raw Interrupt Status Register (see
Register (VICRawIntr - 0xFFFF
The second stage of low-voltage detection asserts Reset to inactivate the LPC2400 when
the voltage on the V
the flash as operation of the various elements of the chip would otherwise become
unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at
which point the Power-On Reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
But when Brown-Out Detection is enabled to bring the LPC2400 out of Power-Down mode
(which is itself not a guaranteed operation -- see
register (PCON - 0xE01F
the Wakeup Timer has completed its delay. In this case, the net result of the transient
BOD is that the part wakes up and continues operation after the instructions that set
Power-Down Mode, without any interrupt occurring and with the BOD bit in the RSID
being 0. Since all other wakeup conditions have latching flags (see
“External Interrupt flag register (EXTINT - 0xE01F C140)”
of this type, without any apparent cause, can be assumed to be a Brown-Out that has
gone away.
Main oscillator enable.
The main oscillator is disabled.
The main oscillator is enabled, and will start up if the correct external
circuitry is connected to the XTAL1 and XTAL2 pins.
Main oscillator status.
The main oscillator is not ready to be used as a clock source.
The main oscillator is ready to be used as a clock source. The main
oscillator must be enabled via the OSCEN bit.
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
F010)”) in order to cause a CPU interrupt; if not, software can monitor the signal
DD(DCDC)(3V3)
Rev. 04 — 26 August 2009
C0C0)”), the supply voltage may recover from a transient before
F008)”).
Section 7–3.4 “Interrupt Enable Register (VICIntEnable -
pins falls below 2.65 V. This Reset prevents alteration of
Section 4–3.4.7 “Power Mode Control
Section 7–3.3 “Raw Interrupt Status
Chapter 3: LPC24XX System control
and
Section
DD(DCDC)(3V3)
Section 3–3.1.2
UM10237
26–6.2), a wakeup
© NXP B.V. 2009. All rights reserved.
Access Reset
R/W
RO
-
pins. If this
39 of 792
value
0
0
NA