LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 402

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
7.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100)
7.3 OTG Interrupt Enable Register (OTGIntEn - 0xFFE0 C104)
7.4 OTG Interrupt Set Register (OTGIntSet - 0xFFE0 C20C)
7.5 OTG Interrupt Clear Register (OTGIntClr - 0xFFE0 C10C)
7.6 OTG Status and Control Register (OTGStCtrl - 0xFFE0 C110)
Bits is this register are set by hardware when the interrupt event occurs during the HNP
handoff sequence. See
Table 364. OTG Interrupt Status register (OTGIntSt - address 0xE01F C100) bit description
Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate
an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT
interrupt line in the USBIntSt register.
The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.
Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.
Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.
Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt
register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in
OTGIntSt.
The OTGStCtrl register allows enabling hardware tracking during the HNP hand over
sequence, controlling the OTG timer, monitoring the timer count, and controlling the
functions mapped to port U1 and U2.
Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:
Bit
0
1
2
3
31:4
1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see
15–7.7 “OTG Timer Register (OTGTmr - 0xFFE0
OTGIntSt, and the timer will be disabled.
Symbol
TMR
REMOVE_PU
HNP_FAILURE
HNP_SUCCESS
-
Rev. 04 — 26 August 2009
Section 15–8
Description
Timer time-out.
Remove pull-up.
This bit is set by hardware to indicate that software
needs to disable the D+ pull-up resistor.
HNP failed.
This bit is set by hardware to indicate that the HNP
switching has failed.
HNP succeeded.
This bit is set by hardware to indicate that the HNP
switching has succeeded.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
for more information on when these bits are set.
Chapter 15: LPC24XX USB OTG controller
C114)”), the TMR bit is set in
UM10237
© NXP B.V. 2009. All rights reserved.
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Section
Reset
Value
0
0
0
0
NA