LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 404

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
7.7 OTG Timer Register (OTGTmr - 0xFFE0 C114)
7.8 OTG Clock Control Register (OTGClkCtrl - 0xFFE0 CFF4)
Table 366. Port function truth table
Table 367. OTG Timer register (OTGTmr - address 0xFFE0 C114) bit description
This register controls the clocking of the OTG controller. Whenever software wants to
access the registers, the corresponding clock control bit needs to be set. The software
does not have to repeat this exercise for every register access, provided that the
corresponding OTGClkCtrl bits are already set.
Table 368. OTG_clock_control register (OTG_clock_control - address 0xFFE0 CFF4) bit
PORT_FUNC[1] = 0
PORT_FUNC[1] = 1
Bit
15:0
31:16 -
Bit
0
Fig 57. Port selection for PORT_FUNC bit 0 = 0 and PORT_FUNC bit 1 = 0.
Symbol
TIMEOUT_CNT The TMR interrupt is set when TMR_CNT reaches this value.
Symbol
HOST_CLK_EN
description
CONTROLLER
CONTROLLER
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
DEVICE
HOST
PORT_FUNC[0] = 0
U1 = device (OTG)
U2 = host
reserved
PORT_FUNC[0] = 0
Value Description
0
1
port1
port1
port2
Host clock enable
Disable the Host clock.
Enable the Host clock.
OTGStCtrl
Chapter 15: LPC24XX USB OTG controller
PORT_FUNC[1] = 0
PORT_FUNC[0] = 1
U1 = host (OTG)
U2 = host
U1 = host
U2 = device
U1
U2
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0xFFFF
NA
404 of 792
Reset
Value
0