LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 405

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
7.9 OTG Clock Status Register (OTGClkSt - 0xFFE0 CFF8)
Table 368. OTG_clock_control register (OTG_clock_control - address 0xFFE0 CFF4) bit
This register holds the clock availability status. When enabling a clock via OTGClkCtrl,
software should poll the corresponding bit in this register. If it is set, then software can go
ahead with the register access. Software does not have to repeat this exercise for every
access, provided that the OTGClkCtrl bits are not disturbed.
Table 369. OTG_clock_status register (OTGClkSt - address 0xFFE0 CFF8) bit description
Bit
1
2
3
4
31:5
Bit
0
1
2
3
Symbol
DEV_CLK_EN
I2C_CLK_EN
OTG_CLK_EN
AHB_CLK_EN
-
Symbol
HOST_CLK_ON
DEV_CLK_ON
I2C_CLK_ON
OTG_CLK_ON
description
Rev. 04 — 26 August 2009
Value Description
0
1
0
1
0
1
0
1
NA
Value Description
0
1
0
1
0
1
0
1
Device clock enable
Disable the Device clock.
Enable the Device clock.
I2C clock enable
Disable the I
Enable the I
OTG clock enable
Disable the OTG clock.
Enable the OTG clock.
AHB master clock enable
Disable the AHB clock.
Enable the AHB clock.
Reserved, user software should not write ones
to reserved bits. The value read from a
reserved bit is not defined.
Host clock status.
Host clock is not available.
Host clock is available.
Device clock status.
Device clock is not available.
Device clock is available.
I2C clock status.
I2C clock is not available.
I2C clock is available.
OTG clock status.
OTG clock is not available.
OTG clock is available.
Chapter 15: LPC24XX USB OTG controller
2
2
C clock.
C clock.
UM10237
© NXP B.V. 2009. All rights reserved.
405 of 792
Reset
Value
0
0
0
0
NA
Reset
Value
0
0
0
0