LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 456
LPC2468FET208,551
Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2468FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S
935283234551
LPC2468FET208-S
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2468FET208,551
Manufacturer:
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Quantity:
6 174
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Part Number:
LPC2468FET208,551
Manufacturer:
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UM10237_4
User manual
4.11 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)
The U1LSR is a read-only register that provides status information on the UART1 TX and
RX blocks.
Table 408. UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit
Bit Symbol
0
1
2
3
4
Receiver
Data
Ready
(RDR)
Overrun
Error
Parity
Error
Framing
Error
Break
Interrupt
(OE)
(PE)
(FE)
(BI)
description
Value Description
0
1
0
1
0
1
0
1
0
1
Rev. 04 — 26 August 2009
U1LSR[0] is set when the U1RBR holds an unread character and
is cleared when the UART1 RBR FIFO is empty.
U1RBR is empty.
U1RBR contains valid data.
The overrun error condition is set as soon as it occurs. An U1LSR
read clears U1LSR[1]. U1LSR[1] is set when UART1 RSR has a
new character assembled and the UART1 RBR FIFO is full. In
this case, the UART1 RBR FIFO will not be overwritten and the
character in the UART1 RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
When the parity bit of a received character is in the wrong state, a
parity error occurs. An U1LSR read clears U1LSR[2]. Time of
parity error detection is dependent on U1FCR[0].
Note: A parity error is associated with the character at the top of
the UART1 RBR FIFO.
Parity error status is inactive.
Parity error status is active.
When the stop bit of a received character is a logic 0, a framing
error occurs. An U1LSR read clears U1LSR[3]. The time of the
framing error detection is dependent on U1FCR0. Upon detection
of a framing error, the RX will attempt to resynchronize to the data
and assume that the bad stop bit is actually an early start bit.
However, it cannot be assumed that the next received byte will be
correct even if there is no Framing Error.
Note: A framing error is associated with the character at the top
of the UART1 RBR FIFO.
Framing error status is inactive.
Framing error status is active.
When RXD1 is held in the spacing state (all 0’s) for one full
character transmission (start, data, parity, stop), a break interrupt
occurs. Once the break condition has been detected, the receiver
goes idle until RXD1 goes to marking state (all 1’s). An U1LSR
read clears this status bit. The time of break detection is
dependent on U1FCR[0].
Note: The break interrupt is associated with the character at the
top of the UART1 RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
Chapter 17: LPC24XX UART1
UM10237
© NXP B.V. 2009. All rights reserved.
456 of 792
Reset
Value
0
0
0
0
0
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