LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 494

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
9. CAN controller operation
UM10237_4
User manual
8.16 Transmit Data Register B (CAN1TDB[1/2/3] - 0xE004 40[3C/4C/5C],
9.1 Error handling
9.2 Sleep mode
CAN2TDB[1/2/3] - 0xE004 80[3C/4C/5C])
When the corresponding TBS bit in CANSR is 1, software can write to one of these
registers to define the 5th through 8th data bytes of the next transmit message. The Data
Length Code defines the number of transferred data bytes. The first bit transmitted is the
most significant bit of TX Data Byte 1.
Table 437. Transmit Data Register B (CAN1TDB[1/2/3] - address 0xE004 40[3C/4C/5C],
The CAN Controllers count and handle transmit and receive errors as specified in CAN
Spec 2.0B. The Transmit and Receive Error Counters are incriminated for each detected
error and are decremented when operation is error-free. If the Transmit Error counter
contains 255 and another error occurs, the CAN Controller is forced into a state called
Bus-Off. In this state, the following register bits are set: BS in CANxSR, BEI and EI in
CANxIR if these are enabled, and RM in CANxMOD. RM resets and disables much of the
CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive
Error Counter is cleared. Software must next clear the RM bit. Thereafter the Transmit
Error Counter will count down 128 occurrences of the Bus Free condition (11 consecutive
recessive bits). Software can monitor this countdown by reading the Tx Error Counter.
When this countdown is complete, the CAN Controller clears BS and ES in CANxSR, and
sets EI in CANxSR if EIE in IER is 1.
The Tx and Rx error counters can be written if RM in CANxMOD is 1. Writing 255 to the
Tx Error Counter forces the CAN Controller to Bus-Off state. If Bus-Off (BS in CANxSR) is
1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When software
clears RM in CANxMOD thereafter, only one Bus Free condition (11 consecutive
recessive bits) is needed before operation resumes.
The CAN Controller will enter sleep mode if the SM bit in the CAN Mode register is 1, no
CAN interrupt is pending, and there is no activity on the CAN bus. Software can only set
SM when RM in the CAN Mode register is 0; it can also set the WUIE bit in the CAN
Interrupt Enable register to enable an interrupt on any wake-up condition.
Bit
7:0
15;8
23:16 Data 7
31:24 Data 8
Symbol Function
Data 5
Data 6
CAN2TDB[1/2/3] - address 0xE004 80[3C/4C/5C]) bit description
If RTR = 0 and DLC
byte is sent as the 5th Data byte of the next transmit message.
If RTR = 0 and DLC
byte is sent as the 6th Data byte of the next transmit message.
If RTR = 0 and DLC
byte is sent as the 7th Data byte of the next transmit message.
If RTR = 0 and DLC
byte is sent as the 8th Data byte of the next transmit message.
Rev. 04 — 26 August 2009
≥
≥
≥
≥
0101 in the corresponding CANTFI, this
0110 in the corresponding CANTFI, this
0111 in the corresponding CANTFI, this
1000 in the corresponding CANTFI, this
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
0
0
0
0
494 of 792
RM
Set
X
X
X
X