LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 496

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
10.2 Central Receive Status Register (CANRxSR - 0xE004 0004)
10.3 Central Miscellaneous Status Register (CANMSR - 0xE004 0008)
Table 438. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description
Table 439. Central Receive Status Register (CANRxSR - address 0xE004 0004) bit
Table 440. Central Miscellaneous Status Register (CANMSR - address 0xE004 0008) bit
Bit
16
17:16 TCS2
31:18 -
Bit
0
1
7:2
8
9
15:10 -
16
17:16 DOS2
31:18 -
Bit
0
1
7:2
Symbol
TCS1
Symbol Description
RS1
RS2
-
RB1
RB2
DOS1
Symbol Description
E1
E2
-
description
description
When 1, CAN1 is receiving a message (same as RS in CAN1GSR).
When 1, CAN2 is receiving a message (same as RS in CAN2GSR).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
When 1, a received message is available in the CAN1 controller (same
as RBS in CAN1GSR).
When 1, a received message is available in the CAN2 controller (same
as RBS in CAN2GSR).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
When 1, a message was lost because the preceding message to CAN1
controller was not read out quickly enough (same as DOS in CAN1GSR).
When 1, a message was lost because the preceding message to CAN2
controller was not read out quickly enough (same as DOS in CAN2GSR).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
When 1, one or both of the CAN1 Tx and Rx Error Counters has reached
the limit set in the CAN1EWL register (same as ES in CAN1GSR)
When 1, one or both of the CAN2 Tx and Rx Error Counters has reached
the limit set in the CAN2EWL register (same as ES in CAN2GSR)
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
When 1, all requested transmissions have been completed successfully
by the CAN1 controller (same as TCS in CAN1GSR).
When 1, all requested transmissions have been completed successfully
by the CAN2 controller (same as TCS in CAN2GSR).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
496 of 792
Reset
Value
0
0
NA
0
0
NA
0
0
NA
Reset
Value
1
1
NA
Reset
Value
0
0
NA