LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 503

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
15.5 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C)
15.6 Extended Frame Group Start Address Register (EFF_GRP_sa -
Table 446. Extended Frame Start Address Register (EFF_sa - address 0xE003 C00C) bit
[1]
0xE003 C010)
Table 447. Extended Frame Group Start Address Register (EFF_GRP_sa - address
[1]
Bit
1:0
10:2
31:11 -
Bit
1:0
11:2
31:12 -
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
Symbol
-
EFF_sa
Symbol
-
Eff_GRP_sa
description
0xE003 C010) bit description
[1]
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
The start address of the table of individual Extended Identifiers in AF
Lookup RAM. If the table is empty, write the same value in this register
and the EFF_GRP_sa register described below. The largest value that
should be written to this register is 0x800, when both Extended Tables
are empty and the last word (address 0x7FC) in AF Lookup Table RAM
is used. For compatibility with possible future devices, please write
zeroes in bits 31:11 and 1:0 of this register.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
[1]
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
The start address of the table of grouped Extended Identifiers in
AF Lookup RAM. If the table is empty, write the same value in this
register and the ENDofTable register described below. The largest
value that should be written to this register is 0x800, when this
table is empty and the last word (address 0x7FC) in AF Lookup
Table RAM is used. For compatibility with possible future devices,
please write zeroes in bits 31:12 and 1:0 of this register.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
503 of 792
Reset
Value
NA
0
NA
Reset
Value
NA
0
NA