LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 527

IC ARM7 MCU FLASH 512K 208TFBGA

LPC2468FET208,551

Manufacturer Part Number
LPC2468FET208,551
Description
IC ARM7 MCU FLASH 512K 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets

Specifications of LPC2468FET208,551

Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2S/ISP/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
6
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
Development Tools By Supplier
OM10100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4262
935283234551
LPC2468FET208-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC2468FET208,551
Manufacturer:
NXP
Quantity:
6 174
Part Number:
LPC2468FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
UM10237_4
User manual
Fig 94. SPI data transfer format (CPHA = 0 and CPHA = 1)
Cycle # CPHA = 0
Cycle # CPHA = 1
MOSI (CPHA = 0)
MISO (CPHA = 0)
MOSI (CPHA = 1)
MISO (CPHA = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
CPHA = 0
CPHA = 1
SSEL
The data and clock phase relationships are summarized in
summarizes the following for each setting of CPOL and CPHA.
Table 459. SPI Data To Clock Phase Relationship
The definition of when an 8 bit transfer starts and stops is dependent on whether a device
is a master or a slave, and the setting of the CPHA variable.
When a device is a master, the start of a transfer is indicated by the master having a byte
of data that is ready to be transmitted. At this point, the master can activate the clock, and
begin the transfer. The transfer ends when the last clock cycle of the transfer is complete.
CPOL and CPHA settings First data driven
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
When the first data bit is driven.
When all other data bits are driven.
When data is sampled.
BIT 1
BIT 1
1
BIT 1
BIT 1
1
BIT 2
BIT 2
2
BIT 2
BIT 2
Rev. 04 — 26 August 2009
2
BIT 3
BIT 3
3
Prior to first SCK rising edge SCK falling edge
First SCK rising edge
Prior to first SCK falling edge SCK rising edge
First SCK falling edge
BIT 3
BIT 3
3
BIT 4
BIT 4
4
BIT 4
BIT 4
4
BIT 5
BIT 5
5
BIT 5
BIT 5
5
BIT 6
BIT 6
6
BIT 6
BIT 6
6
Other data driven Data sampled
SCK rising edge
SCK falling edge
BIT 7
BIT 7
7
BIT 7
BIT 7
Table
7
Chapter 19: LPC24XX SPI
BIT 8
BIT 8
8
19–459. This table
BIT 8
BIT 8
8
UM10237
© NXP B.V. 2009. All rights reserved.
SCK rising edge
SCK falling edge
SCK falling edge
SCK rising edge
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