LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 53

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
3.2.10 PLL and Power-down mode
3.2.11 PLL frequency calculation
3.2.9 PLL Feed register (PLLFEED - 0xE01F C08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
The two writes must be in the correct sequence, and must be consecutive APB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
Table 49.
Power-down mode automatically turns off and disconnects the PLL. Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
The PLL equations use the following parameters:
Table 50.
The PLL output frequency (when the PLL is both active and connected) is given by:
F
The PLL inputs and settings must meet the following:
The PLL equation can be solved for other PLL parameters:
Bit
7:0
Parameter
F
F
N
M
F
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
CCO
•
•
IN
CCO
REF
F
F
IN
CCO
= (2 × M × F
Symbol
PLLFEED The PLL feed sequence must be written to this register in order for
is in the range of 32 kHz to 50 MHz.
is in the range of 275 MHz to 550 MHz.
PLL Feed register (PLLFEED - address 0xE01F C08C) bit description
PLL frequency parameter
IN
Description
the frequency of pllclkin from the Clock Source Selection Multiplexer.
the frequency of the pllclk (output of the PLL Current Controlled Oscillator)
PLL Pre-divider value from the NSEL bits in the PLLCFG register (PLLCFG
NSEL field + 1). N is an integer from 1 through 32.
PLL Multiplier value from the MSEL bits in the PLLCFG register (PLLCFG
MSEL field + 1). Not all potential values are supported. See below.
PLL internal reference frequency, FIN divided by N.
Description
PLL configuration and control register changes to take effect.
) / N
Rev. 04 — 26 August 2009
Chapter 4: LPC24XX Clocking and power control
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0x00