LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 55

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
3.2.13 Examples of PLL settings
In general, it is better to use a smaller value for N, to reduce the level of multiplication that
must be accomplished by the CCO. Due to the difficulty in finding the best values in some
cases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet is
available from NXP for this purpose.
The following examples illustrate selecting PLL values based on different system
requirements.
Example 1)
Assumptions:
Calculations:
M = (F
Start by assuming N = 1, since this produces the smallest multiplier needed for the PLL.
So, M = 288 × 10
look further for a good set of PLL configuration values. The value written to PLLCFG
would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23).
The potential CPU clock rate can be determined by dividing F
frequency: 288 × 10
Divider is then 5, giving us 57.6 MHz as the nearest value to the desired CPU clock rate.
If it is important to obtain exactly 60 MHz, an F
down to both 48 MHz and 60 MHz. The only possibility is 480 MHz. Divided by 10, this
gives the 48 MHz with a 50% duty cycle needed by the USB block. Divided by 8, it gives
60 MHz for the CPU clock. PLL settings for 480 MHz are N = 1 and M = 60.
Example 2)
Assumptions:
Calculations:
3. Choose a value for the PLL input frequency (F
4. Calculate values for M and N to produce a sufficiently accurate F
•
•
•
•
•
•
the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used.
desired M value -1 will be written to the MSEL field in PLLCFG. The desired N value -1
will be written to the NSEL field in PLLCFG.
The USB interface will be used in the application. The lowest integer multiple of
96 MHz that falls within the PLL operating range (288 MHz) will be targeted.
The desired CPU rate = 60 MHz.
An external 4 MHz crystal or clock source will be used as the system clock source.
The USB interface will not be used in the application.
The desired CPU rate = 72 MHz
The 32.768 kHz RTC clock source will be used as the system clock source
CCO
× N) / (2 × F
6
/ (2 × 4 × 10
6
/ 60 × 10
Rev. 04 — 26 August 2009
IN
)
6
6
) = 36. Since the result is an integer, there is no need to
= 4.8. The nearest integer value for the CPU Clock
Chapter 4: LPC24XX Clocking and power control
CCO
IN
rate must be found that can be divided
). This can be a clock obtained from
CCO
by the desired CPU
CCO
UM10237
© NXP B.V. 2009. All rights reserved.
frequency. The
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