LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 56

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
3.2.14 PLL setup sequence
M = (F
The smallest frequency for F
within the PLL operating range is 288 MHz (4 × 72 MHz). Start by assuming N = 1, since
this produces the smallest multiplier needed for the PLL.
So, M = 288 × 10
frequency will not be exactly 288 MHz with this setting. Since this case is less obvious, it
may be useful to make a table of possibilities for different values of N (see
Table 52.
Beyond N = 7, the value of M is out of range or not supported, so the table stops there. In
the table, the calculated M value is rounded to the nearest integer. If this results in CCLK
being above the maximum operating frequency (72 MHz), it is allowed if it is not more than
1/2 % above the maximum frequency.
In general, larger vlaues of F
frequency. Even the first table entry shows a very small error of just over 1 hundredth of a
percent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm.
Remember that when a frequency below about 1 MHz is used as the PLL clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
Table 4–52
If PLL calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit. Multiplier values one count off
from calculated values may also be good possibilities..
The value written to PLLCFG for the second table entry would be 0x12254
(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).
The following sequence must be followed step by step in order to have the PLL initialized
an running:
N
1
2
3
4
5
1. Disconnect the PLL with one feed sequence if PLL is already connected.
2. Disable the PLL with one feed sequence.
3. Change the CPU Clock Divider setting to speed up operation without the PLL, if
4. Write to the Clock Source Selection Control register to change the clock source.
5. Write to the PLLCFG and make it effective with one feed sequence. The PLLCFG can
desired.
only be updated when the PLL is disabled.
M
4394.53125
8789.0625
13183.59375
17578.125
21972.65625
CCO
Potential values for PLL example
× N) / (2 × F
of this exmaple are supported, as may be confirmed in
6
/ (2 × 32,768) = 4,394.53125. This is not an integer, so the CPU
M Rounded F
4395
8789
13184
17578
21973
Rev. 04 — 26 August 2009
IN
)
CCO
REF
32768
16384
10922.67
8192
6553.6
result in a more stable PLL when the input clock is a low
that can produce our desired CPU clock rate and is
REF
Chapter 4: LPC24XX Clocking and power control
(Hz)
F
288.0307
287.9980
288.0089
287.9980
288.0045
CCO
(MHz)
Actual
CCLK (MHz)
72.0077
71.9995
72.0022
71.9995
72.0011
Table
UM10237
© NXP B.V. 2009. All rights reserved.
4–51.
Table
% Error
0.0107
-0.0007
0.0031
-0.0007
0.0016
4–52).
56 of 792