LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 561

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
5.3.12 CRC generator
5.3.13 Data FIFO
5.3.11 Status flags
Table 21–487
(MCIStatus - 0xE008 C034)” on page 569
Table 487. Data path status flags
The CRC generator calculates the CRC checksum only for the data bits in a single block,
and is bypassed in data stream mode. The checksum is a 16 bit value:
The data FIFO (first-in-first-out) subunit is a data buffer with transmit and receive logic.
The FIFO contains a 32 bit wide, 16-word deep data buffer, and transmit and receive
logic. Because the data FIFO operates in the APB clock domain (PCLK), all signals from
the subunits in the MCI clock domain (MCLK) are resynchronized.
Depending on TxActive and RxActive, the FIFO can be disabled, transmit enabled, or
receive enabled. TxActive and RxActive are driven by the data path subunit and are
mutually exclusive:
Flag
TxFifoFull
TxFifoEmpty
TxFifoHalfEmpty
TxDataAvlbl
TxUnderrun
RxFifoFull
RxFifoEmpty
RxFifoHalfFull
RxDataAvlbl
RxOverrun
DataBlockEnd
StartBitErr
DataCrcFail
DataEnd
DataTimeOut
TxActive
RxActive
•
CRC[15:0] = Remainder [(M(x) × x
G(x) = x
M(x) - (first data bit) × x
The transmit FIFO refers to the transmit logic and data buffer when TxActive is
asserted (see
16
+ x
lists the data path status flags (see
12
Section 21–5.3.14 “Transmit
+ x
5
Rev. 04 — 26 August 2009
+ 1
n
+ ... + (last data bit) ¥ X
Description
Transmit FIFO is full.
Transmit FIFO is empty.
Transmit FIFO is half full.
Transmit FIFO data available.
Transmit FIFO underrun error.
Receive FIFO is full.
Receive FIFO is empty.
Receive FIFO is half full.
Receive FIFO data available.
Receive FIFO overrun error.
Data block sent/received.
Start bit not detected on all data signals in wide bus mode.
Data packet CRC failed.
Data end (data counter is zero).
Data timeout.
Data transmission in progress.
Data reception in progress.
15
) / G(x)]
Chapter 21: LPC24XX SD/MMC card interface
for more information).
FIFO”)
Section 21–6.11 “Status Register
0
UM10237
© NXP B.V. 2009. All rights reserved.
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