LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 562

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
5.3.14 Transmit FIFO
5.3.15 Receive FIFO
Data can be written to the transmit FIFO through the APB interface once the MCI is
enabled for transmission.
The transmit FIFO is accessible via 16 sequential addresses (see
FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008
a data output register that holds the data word pointed to by the read pointer. When the
data path subunit has loaded its shift register, it increments the read pointer and drives
new data out.
If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit
asserts TxActive when it transmits data.
Table 488. Transmit FIFO status flags
When the data path subunit receives a word of data, it drives data on the write data bus
and asserts the write enable signal. This signal is synchronized to the PCLK domain. The
write pointer is incremented after the write is completed, and the receive FIFO control
logic asserts RxWrDone, that then deasserts the write enable signal.
On the read side, the content of the FIFO word pointed to by the current value of the read
pointer is driven on the read data bus. The read pointer is incremented when the APB bus
interface asserts RxRdPrtInc.
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data. Table
353 lists the receive FIFO status flags.
The receive FIFO is accessible via 16 sequential addresses (see
FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data.
Table 21–489
Flag
TxFifoFull
TxFifoEmpty
TxHalfEmpty
TxDataAvlbl
TxUnderrun
•
The receive FIFO refers to the receive logic and data buffer when RxActive is
asserted (see
lists the receive FIFO status flags.
Section 21–5.3.15 “Receive
Rev. 04 — 26 August 2009
Description
Set to HIGH when all 16 transmit FIFO words contain valid data.
Set to HIGH when the transmit FIFO does not contain valid data.
Set to HIGH when 8 or more transmit FIFO words are empty. This flag
can be used as a DMA request.
Set to HIGH when the transmit FIFO contains valid data. This flag is the
inverse of the TxFifoEmpty flag.
Set to HIGH when an underrun error occurs. This flag is cleared by
writing to the MCIClear register.
Table 21–488
Chapter 21: LPC24XX SD/MMC card interface
FIFO”).
C0BC)”). The transmit FIFO contains
C0BC)”).
lists the transmit FIFO status flags.
Section 21–6.15 “Data
Section 21–6.15 “Data
UM10237
© NXP B.V. 2009. All rights reserved.
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