LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 581

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
8. Register description
Table 512. Summary of I
UM10237_4
User manual
Generic
Name
I2CONSET I2C Control Set Register. When a one is written to a
I2STAT
I2DAT
I2ADR
Description
bit of this register, the corresponding bit in the I
control register is set. Writing a zero has no effect on
the corresponding bit in the I
I2C Status Register. During I
register provides detailed status codes that allow
software to determine the next action needed.
I2C Data Register. During master or slave transmit
mode, data to be transmitted is written to this register.
During master or slave receive mode, data that has
been received may be read from this register.
I2C Slave Address Register. Contains the 7 bit slave
address for operation of the I
mode, and is not used in master mode. The least
significant bit determines whether a slave responds to
the general call address.
7.9 Status decoder and status register
The contents of the I
will set bits in the I
Conversely, writing to I2CONCLR will clear bits in the I
to ones in the value written.
The status decoder takes all of the internal status bits and compresses them into a 5 bit
code. This code is unique for each I
vector addresses for fast processing of the various service routines. Each service routine
processes a particular bus status. There are 26 possible bus states if all four modes of the
I
status register when the serial interrupt flag is set (by hardware) and remains stable until
the interrupt flag is cleared by software. The three least significant bits of the status
register are always zero. If the status code is used as a vector to service routines, then the
routines are displaced by eight address locations. Eight bytes of code is sufficient for most
of the service routines (see the software example in this section).
Each I
2
2
C block are used. The 5 bit status code is latched into the five most significant bits of the
C registers
2
C interface contains 7 registers as shown in
2
2
C control register.
2
C interface in slave
C operation, this
2
C control register that correspond to ones in the value written.
2
C control register may be read as I2CONSET. Writing to I2CONSET
Rev. 04 — 26 August 2009
2
C
2
C bus status. The 5 bit code may be used to generate
Access Reset
R/W
RO
R/W
R/W
Chapter 22: LPC24XX I
value
0x00
0xF8
0x00
0x00
Table 22–512
[1]
2
C control register that correspond
I
Name & Address
I2C0CONSET - 0xE001 C000
I2C1CONSET - 0xE005 C000
I2C2CONSET - 0xE008 0000
I2C0STAT - 0xE001 C004
I2C1STAT - 0xE005 C004
I2C2STAT - 0xE008 0004
I2C0DAT - 0xE001 C008
I2C1DAT - 0xE005 C008
I2C2DAT - 0xE008 0008
I2C0ADR - 0xE001 C00C
I2C1ADR - 0xE005 C00C
I2C2ADR - 0xE008 000C
2
Cn Register
below.
2
C interfaces I
UM10237
© NXP B.V. 2009. All rights reserved.
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2
C0/1/2