LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 585

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
8.4 I
8.5 I
8.6 I
8.7 I
8.8 Selecting the appropriate I
0xE008 0008)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
Table 516. I
0xE005 C00C, 0xE008 000C)
These registers are readable and writable, and is only used when an I
slave mode. In master mode, this register has no effect. The LSB of I2ADR is the general
call bit. When this bit is set, the general call address (0x00) is recognized.
Table 517. I
0xE005 C010, 0xE008 0010)
Table 518. I
0xE005 C014, 0xE008 0014)
Table 519. I
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of PCLK cycles for the SCL high
time, I2SCLL defines the number of PCLK cycles for the SCL low time. The frequency is
determined by the following formula (f
Bit Symbol
7:0 Data
Bit Symbol
0
7:1 Address
Bit
15:0
Bit
15:0
2
2
2
2
C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008,
C Slave Address Register (I2C[0/1/2]ADR - 0xE001 C00C,
C SCL High Duty Cycle Register (I2C[0/1/2]SCLH - 0xE001 C010,
C SCL Low Duty Cycle Register (I2C[0/1/2]SCLL - 0xE001 C014,
GC
Symbol
SCLH
Symbol
SCLL
0xE008 0008) bit description
0xE005 C00C, 0xE008 000C) bit description
0xE005 C010, 0xE008 0010) bit description
0xE005 C014, 0xE008 0014) bit description
2
2
2
2
C Data Register ( I2C[0/1/2]DAT - addresses 0xE001 C008, 0xE005 C008,
C Slave Address register (I2C[0/1/2]ADR - addresses 0xE001 C00C,
C SCL High Duty Cycle register (I2C[0/1/2]SCLH - addresses 0xE001 C010,
C SCL Low Duty Cycle register (I2C[0/1/2]SCLL - addresses 0xE001 C014,
Description
This register holds data values that have been received, or are to
be transmitted.
Description
General Call enable bit.
The I
Description
Count for SCL HIGH time period selection.
Description
Count for SCL LOW time period selection.
2
C device address for slave mode.
Rev. 04 — 26 August 2009
2
C data rate and duty cycle
PCLK
Chapter 22: LPC24XX I
being the frequency of PCLK):
2
C interfaces I
2
UM10237
C interface is set to
© NXP B.V. 2009. All rights reserved.
Reset Value
0x0004
Reset Value
0x0004
Reset Value
0
Reset Value
0
0x00
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2
C0/1/2