LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 586

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
9. Details of I
UM10237_4
User manual
2
The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I
specification defines the SCL low time and high time at different values for a 400 kHz I
rate. The value of the register must ensure that the data rate is in the I
of 0 through 400 kHz. Each register value must be greater than or equal to 4.
Table 22–520
I2SCLL and I2SCLH values.
Table 520. Example I
The four operating modes are:
Data transfers in each mode of operation are shown in Figures
lists abbreviations used in these figures when describing the I
Table 521. Abbreviations used to describe an I
C operating modes
I2SCLL +
I2SCLH
8
10
25
50
100
160
200
400
800
Abbreviation
S
SLA
R
W
A
•
•
•
•
Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter
1
125
100
40
20
10
6.25
5
2.5
1.25
gives some examples of I
2
C Clock Rates
Rev. 04 — 26 August 2009
Explanation
Start Condition
7 bit slave address
Read bit (high level at SDA)
Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
5
200
100
50
31.25
25
12.5
6.25
I 2 C
bitfrequency
I
2
C Bit Frequency (kHz) at PCLK (MHz)
10
400
200
100
62.5
50
25
12.5
2
=
C bus rates based on PCLK frequency and
Chapter 22: LPC24XX I
-------------------------------------------------------- -
I2CSCLH
16
320
160
100
80
40
20
2
C operation
f
PCLK
+
I2CSCLL
20
400
200
100
25
125
50
2
C operating modes.
120
2
40
400
250
200
100
50
C interfaces I
to 124.
UM10237
2
© NXP B.V. 2009. All rights reserved.
C data rate range
Table 22–521
2
C bus
60
375
300
150
75
586 of 792
2
C0/1/2
(12)
2
C