LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 588

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

NXP Semiconductors
UM10237_4
User manual
9.2 Master Receiver mode
9.3 Slave Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see
the start condition has been transmitted, the interrupt service routine must load I2DAT with
the 7 bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then
be cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in
After a repeated start condition (state 0x10), the I
transmitter mode by loading I2DAT with SLA+W.
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see
loaded as follows:
Table 523. I2C0ADR and I2C1ADR usage in Slave Receiver mode
The upper 7 bits are the address to which the I
master. If the LSB (GC) is set, the I
(0x00); otherwise it ignores the general call address.
Table 524. I2C0CONSET and I2C1CONSET used to initialize Slave Receiver mode
The I
to logic 1 to enable the I
acknowledge its own slave address or the general call address. STA, STO, and SI must
be reset.
When I2ADR and I2CON have been initialized, the I
its own slave address followed by the data direction bit which must be “0” (W) for the I
block to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag (SI) is set and a valid status code can be read
from I2STAT. This status code is used to vector to a state service routine. The appropriate
action to be taken for each of these status codes is detailed in
receiver mode may also be entered if arbitration is lost while the I
mode (see status 0x68 and 0x78).
Bit
Symbol
Bit
Symbol
Value
Figure
Figure
2
C bus rate settings do not affect the I
7
7
-
-
22–121). The transfer is initialized as in the master transmitter mode. When
22–122). To initiate the slave receiver mode, I2ADR and I2CON must be
6
6
I2EN
1
Rev. 04 — 26 August 2009
2
C block. The AA bit must be set to enable the I
5
5
STA
0
own slave 7 bit address
2
C block will respond to the general call address
4
4
STO
0
Chapter 22: LPC24XX I
2
C block in the slave mode. I2EN must be set
2
C block will respond when addressed by a
2
C block may switch to the master
3
3
SI
0
2
C block waits until it is addressed by
2
2
AA
1
Table
2
C block is in the master
2
C interfaces I
22–527. The slave
UM10237
1
1
-
-
© NXP B.V. 2009. All rights reserved.
2
C block to
Table
0
GC
0
-
-
22–526.
588 of 792
2
C0/1/2
2
C